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 Post subject: CPLD codecheck
PostPosted: Wed May 29, 2019 9:43 pm 
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Joined: Sun Sep 08, 2013 10:24 am
Posts: 740
Location: A missile silo somewhere under southern England
Hey guys

I'm currently writing a CPLD (Atmel ATF1504AS) to select a paged ROM or a paged RAM bank (8 in a 1mbit SRAM) on a BBC Micro (6502A cpu). I've written the following wincupl code, but am finding that FIELD/TABLE part is not giving the correct output.
Woud someone familar with wincupl be able to take a look as I cannot see what is wrong (despite looking at it for days) and feel that a fresh set of eyes might spot the issue. I'm not asking if it will do the job as intended, but just asking if I've made a syntax-like mistake.



Code:
Name      BeebSWR;
Partno    C;
Date      27/4/2018;
Rev       01;
Designer  Mike;
Company   shalewyn.com;
Assembly  None;
Location  None;
Device    f1504ispplcc44;


/* INPUTS */
Pin 12 = nROMsel;      /* /ROMSEL signal from the beeb. When it goes low then &FE30 is being written to. This is inputted here so it can be inverted and output via ROMsel */
Pin [29..26] = [D3..0];   /* Ouputs from the latch. Used to select the ROM whn /ROMsel goes low on the beeb */

Pin 36 = beebA15;      /* A14 and A15 address lines from the beeb. Used to determine if &8000 to&BFFF is being accessed */
Pin 37 = beebA14;

Pin 33 = WriteProtect;   /* SRAM write protect line. If held high then SRAM cab be written to */
Pin 34 = beebRW;      /* R/W signal from the beeb */


/* OUTPUTS */
Pin 24 = ROMsel;   /* Invert /ROMselsignal from the beeb. Used to latch D0-D3 - i.e. the ROM bing selected when &FE30 is being written to */

Pin 16 = ramA16;   /* A14-A16 on the SRAM. Used to select the bank to be used */
Pin 17 = ramA15;
Pin 18 = ramA14;

Pin 19 = ramCE;   /* SRAM chip enable. active low */
Pin 20 = ramWE;   /* SRAM write enable. active low */
Pin 21 = ramOE;   /* SRAM output (read) enable. active low */

Pin 9 = s21sw;
Pin 8 = useSRAM;   /* held high if beeb socket roms should be used, low if SRAM */
Pin 40 = useBeeb;   /* held high if no ROM is selectable, low if  */


/* MAIN */
ROMsel = !nROMsel;

FIELD BankSelect = [D3..0];
FIELD AddressSelects = [ramA16,ramA15,ramA14,useSRAM,useBeeb];
TABLE BankSelect => AddressSelects {
   [C..F] => 0b000101;   /* sockets 12 to 15 - beeb ROM physical sockets */
   [B..B] => 0b000010;   /* socket 11, SRAM */
   [A..A] => 0b001010;   /* socket 10, SRAM */
   [9..9] => 0b010010;   /* socket 9, SRAM */
   [8..8] => 0b100010;   /* socket 8, SRAM */
   [7..7] => 0b110010;   /* socket 7, SRAM */
   [6..6] => 0b011010;   /* socket 6, SRAM */
   [5..5] => 0b101010;   /* socket 5, SRAM */
   [4..4] => 0b111010;   /* socket 4, SRAM */
   [0..3] => 0b000000;   /* sockets 0 to 3, not used */
}

/* determine if &8000 to &BFFF is being accessed and if so whether to enable the SRAM or the sockets on the beeb
   !ramCE conrols the enable pin on the SRAM and s21sw connected to the enble on IC20 on the beeb. Both are active low */
!ramCE = useSRAM & beebA14 & !beebA15;
!s21sw = useBeeb & beebA14 & !beebA15;

/* if SRam being accessed then either enable output or enable writing. If enabling writing then check if protection
   signal allows this */
!ramOE = ramCE & beebRW;
!ramWE = ramCE & !beebRW & WriteProtect;


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 Post subject: Re: CPLD codecheck
PostPosted: Thu May 30, 2019 4:40 pm 
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Joined: Sat Jan 02, 2016 10:22 am
Posts: 197
Could it be this ?
Code:
FIELD AddressSelects = [ramA16,ramA15,ramA14,useSRAM,useBeeb];

You're defining 5 bits, but setting 6 ?
Code:
   [C..F] => 0b000101;   /* sockets 12 to 15 - beeb ROM physical sockets */


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 Post subject: Re: CPLD codecheck
PostPosted: Thu May 30, 2019 5:42 pm 
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Joined: Sun Sep 08, 2013 10:24 am
Posts: 740
Location: A missile silo somewhere under southern England
lol yes indeed - was from previous testing. I spotted that earlier and have been testing after changing it. However, still getting issues.\
"useSRAM" and "useBeeb" will go high with the other low (or vice versa) apart from when D0-3 gives a result of 0 to 3 (0000-0011). However, although useBeeb chnages as needed now, useSRAM (pin 8 ) stays low no matter what. Going by the datasheet. pin 8 is just a standard I/O pin.


Code:
FIELD BankSelect = [D3..0];
FIELD AddressSelects = [ramA16,ramA15,ramA14,useSRAM,useBeeb];
TABLE BankSelect => AddressSelects {
   [C..F] => 0b00001;   /* 12 to 15 - ROM sockets */
   [B..B] => 0b00010;   /* 11 */
   [A..A] => 0b00110;   /* 10 */
   [9..9] => 0b01010;   /*  9 */
   [8..8] => 0b10010;   /*  8 */
   [7..7] => 0b11010;   /*  7 */
   [6..6] => 0b01110;   /*  6 */
   [5..5] => 0b10110;   /*  5 */
   [4..4] => 0b11110;   /*  4 */
   [0..3] => 0b00000;   /*  0 to 3 */
}


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 Post subject: Re: CPLD codecheck
PostPosted: Thu May 30, 2019 7:48 pm 
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Joined: Sun Sep 08, 2013 10:24 am
Posts: 740
Location: A missile silo somewhere under southern England
*sigh* It's the simple things that get you. Such as using 0b to denote a binary pattern when you should use 'b' ...

Code:
FIELD BankSelect = [D0..3];
FIELD AddressSelects = [ramA16,ramA15,ramA14,useSRAM,useBeeb];
TABLE BankSelect => AddressSelects {
   [C..F] => 'b'00001;   /* 12 to 15 - ROM sockets */
   [B..B] => 'b'00010;   /* 11 */
   [A..A] => 'b'00110;   /* 10 */
   [9..9] => 'b'01010;   /*  9 */
   [8..8] => 'b'10010;   /*  8 */
   [7..7] => 'b'11010;   /*  7 */
   [6..6] => 'b'01110;   /*  6 */
   [5..5] => 'b'10110;   /*  5 */
   [4..4] => 'b'11110;   /*  4 */
   [0..3] => 'b'00000;   /*  0 to 3 */


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