dmsc wrote:
Comparing with my own project at
https://github.com/dmsc/my6502 , you implemented a few thinks differently:
Yes - I started with a system architecture that was based strongly on the old OSI Superboard.
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- You have the video RAM separated from CPU RAM and access through the video module, I have unified RAM.
Yes - that's how the Superboard video worked so I just stuck with that partitioning. Using a separate SPRAM for video allows me to do some paging tricks without disturbing the main memory.
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- I simply clock the RAM at twice the CPU frequency, and access through the CPU on even cycles and through the video on odd cycles.
That's not a bad way to do it, but it involves a bit more effort in setting up clock domains and maintaining synchronism. It was initially easier for me to go with a single clock domain for the entire system, but then that ended up requiring arbitration logic to keep CPU and Video DMA from contending. In retrospect I might reconsider the approach you took. Since my video memory is isolated it wouldn't be hard to change, but I would need to rework the top-level clocking architecture a bit to supply the 2x clock.
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- My internal bus is somewhat simpler, I only pass a "we" signal to peripherals, so all peripherals are read in every CPU cycle.
That's not too different from my approach - I pass a WE and select line to every peripheral, but the default is to read and there's one big mux to route the correct target address back to the CPU.
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I also use a STM32 as programmer, using a bluepill board with "serprog" protocol,
https://github.com/dmsc/stm32-vserprog and ported iceprog to use the same
https://github.com/dmsc/iceprog-serprog .
That's neat. I made a custom STM32F042 board that handles the SPI protocol for the FPGA. I'd like to extend it to handling the Flash programming as well - for now I have to "borrow" the FTDI interface from a Lattice Devboard. I'd also like to add a USB/Serial function to my board, but that requires learning how composite USB devices work so I've put it off.
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I plan to port my FastBasic IDE to the board, this will provide a simple full screen environment with graphics.
Fun! So far I'm just coding either in ca65 which gets loaded into my "ROM", or in the old MS BASIC. I've got SPI access to the FPGA configuration flash memory working, so now I need to code up some read/write routines to tie into the exiting LOAD/SAVE hooks in the old code.