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xjmaas
PostPosted: Mon Jun 04, 2018 5:21 pm 
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Hi,

I am trying to get some 6502-core based computer running on my Mojo V3. It seems I can free run the CPU, can read the ROM (right now a core-IP ROM in the bitstream). It is based on the project(s) by Grant Searle, however I cannot get any serial communication working using the supplied AVR on the board. (I also lack a UART cable, still). I would really like to implement a simple serial interface, so I can communicate with my board (thus the 6502).
The project will be made in VHDL (which I am also learning at the moment).
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kakemoms
PostPosted: Mon Jun 11, 2018 8:32 am 
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xjmaas wrote:
Hi,

I am trying to get some 6502-core based computer running on my Mojo V3. It seems I can free run the CPU, can read the ROM (right now a core-IP ROM in the bitstream). It is based on the project(s) by Grant Searle, however I cannot get any serial communication working using the supplied AVR on the board. (I also lack a UART cable, still). I would really like to implement a simple serial interface, so I can communicate with my board (thus the 6502).
The project will be made in VHDL (which I am also learning at the moment).


Well, the easiest to tie with a 6502 is a 6522. WDC65C22 for example. You don't say much about which type of serial communication you want, and for RS232 or alike you will need a level shifter of some sort (232 usually communicates at higher voltages than the stock 6502/6522). If you want USB, I would connect a FTDI232 to the 6522.
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xjmaas
PostPosted: Tue Jun 12, 2018 9:33 am 
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The Mojo V3 has an AVR on board which can be used for the serial connection. You are right I can use a 6522 (physical IC), but I would like to use the AVR based serial connection. The 6502 is a core in the FPGA.
I have the 6502 core running, with RAM and ROM also in the FPGA (I can run a simple test ROM program and follow address and data lines using 7-segment displays).
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xjmaas
PostPosted: Mon Jun 18, 2018 12:05 pm 
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I did some more testing, running at 2Hz (so I can easily follow the code), gives me many repeated characters, but somehow the message is shown. When bumping the speed to 2MHz, I loose some characters (@random).
I am now running the implementation at 1MHz, and the message is shown correctly (right now only text output over serial is implemented).

(I can post the source somewhere is someone is interested, or wants to help me understand better ;))
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GaBuZoMeu
PostPosted: Mon Jun 18, 2018 1:06 pm 
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Of course I don't know the details - how should I without sources ;). But if your messages are sent correctly @ 1MHz but not @ 2MHz I assume that you either have no handshake between the FPGA and the AVR established or the handshake don't work as it should. If the AVR serial interface you are using is UART or USI based, you may change the baudrate there to verify what happens. If you lower the baudrate say to 1200 baud or less (I assume you use 9600 Bd or more) then loosing characters @ 1MHz could occur if your FPGA simply "overruns" the AVR.

As I don't know how the FPGA and the AVR are communicate with each other (SPI?, parallel?, else?) there are more possibilities were things might went wrong.


Regards.
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xjmaas
PostPosted: Tue Jun 19, 2018 8:08 am 
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I just uploaded the Xilinx ISE project to my website
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GaBuZoMeu
PostPosted: Tue Jun 19, 2018 11:01 am 
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Perhaps you can submit the (commented?)°° ASM source of your test program - "reading" .MIF is cumbersome ;)


_____________
°°: I know, there is only one logic relation between writing code and commenting - its XOR :lol:
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xjmaas
PostPosted: Tue Jun 19, 2018 4:26 pm 
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GaBuZoMeu wrote:
Perhaps you can submit the (commented?)°° ASM source of your test program - "reading" .MIF is cumbersome ;)


This is my test code, assembled with ca65.

Code:
.segment "EXEHDR"
.segment "STARTUP"

.linecont +

; We map the serial device at $C000 for easy memory mapping?
      .org   $F000
      
ACIA       :=   $C000
ACIAControl :=    ACIA+0
ACIAStatus    :=    ACIA+0
ACIAData    :=    ACIA+1
      
start:
      ldx   #$00
      txs
      lda   #$95            ; Set ACIA baud rate, word size and Rx interrupt (RTS)
                        ; which is not needed right now, but taken from Grant's
                        ; example
      sta ACIAControl
; Show message
      ldy #$00
showmsg:
      lda   message,Y
      beq done
      jsr uartout
      iny
      jmp showmsg
      
done:                     ; Loop ;))
      jmp done

uartout:
      pha
SerialOutWait:
      lda ACIAStatus
      and #$02
      cmp #$02
      bne SerialOutWait
      pla
      and #%01111111         ; Make sure to use low ascii
      sta ACIAData
      rts
      brk
      brk
      
message:
      .byte "Welcome to my FPGA", $0D, $00
      
      .res   $FFF8-*, $EA   ; Just to be sure, all NOPs until
                        ; RESET/IRQ vectors
                        
; We should enter the RESET/IRQ vectors here
; Right now they all point to the same address
ABORT:   .addr   $F000         ; Should be at $FFF8/FFF9
NMI:   .addr   $F000         ; $FFFA/$FFFB
RESET:   .addr   $F000         ; $FFFC/$FFFD
IRQ:   .addr   $F000         ; $FFFE/$FFFF
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GaBuZoMeu
PostPosted: Tue Jun 19, 2018 8:16 pm 
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Could it be that the ACIA baud rate doubles when you double the system clock?

What is the baud rate when you initialize your virtual ACIA with $95 ?

BTW: after

lda ACIAstatus
and #$02

there are only two possible results: 0 or 2
so continuing with

beq SerialOutWait

would save one instruction ;)

EDIT: typo

P.S.: Your code checks that TX is empty, then immediately issuing the next character. If for any reason (and somewhat unlikely) the AVR could not process the received characters quickly enough an overrun condition could occur.
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xjmaas
PostPosted: Wed Jun 20, 2018 6:02 am 
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GaBuZoMeu wrote:
Could it be that the ACIA baud rate doubles when you double the system clock?

What is the baud rate when you initialize your virtual ACIA with $95 ?


The baud rate is set in the AVRuart and is set to 100 clock cycles per bit (500000), which is per example of embeddedmicro. So no 'real' baud setting, yet.

GaBuZoMeu wrote:
BTW: after

lda ACIAstatus
and #$02

there are only two possible results: 0 or 2
so continuing with

beq SerialOutWait

would save one instruction ;)


It is actually in preparation for more tests of the ACIAstatus register in the future(?)

GaBuZoMeu wrote:
EDIT: typo

P.S.: Your code checks that TX is empty, then immediately issuing the next character. If for any reason (and somewhat unlikely) the AVR could not process the received characters quickly enough an overrun condition could occur.


If the AVR's buffer is full, tx_block should be high, which is a physical pin from the AVR to the FPGA
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GaBuZoMeu
PostPosted: Wed Jun 20, 2018 6:26 am 
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Most likely you can increase the number of missing characters when you set the baud rate higher (not 100 cycles/bit but e.g. 20). Perhaps the mechanism that should block the transmission if the AVR is busy won't work automatically or requires software attention (checking more than only TXempty).

Or you greatly slow down the communication speed (say 5000 cycles/bit). Then your AVR should keep up with the 6502 even when the 6502 is running with 5 or 10 MHz.

I think it is easy to try this out. If my assumptions are right, you should remember that there is work to be done around tx_block. :)
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xjmaas
PostPosted: Wed Jun 20, 2018 2:39 pm 
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Thanks,

I'll have a look at it this week.
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xjmaas
PostPosted: Tue Jun 26, 2018 9:13 am 
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Seems I had to RTFM... there is no RTS support from the AVR on the Mojo to the FPGA.

So, I had to order an USB-UART cable (3.3V). I rebuilt the test project and the test print routine works...

Thanks for the suport
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