Hi,

On my board I have RDY pulled high with a 3k3 resistor, RDY is also connected to a pin of my CPLD and nothing else.

What I've noticed is that the signal rises so slowly after being high-z'ed by the CPLD that the CPU is effectively halted completely.

(RDY is top, PHI2 is bottom)

If I drive the signal high it works, but being a bi-directional signal this is not the best idea


I'm just driving it with a simple flip-flop at the moment for testing, the VHDL is


Shouldn't the signal rise much faster? I've tried changing the turbo bit setting (fast/slow slew rate) but it didn't make a difference to this.

Looks like you have quite a large capacitance on this line, roughly 100pF which is 5 times higher than usual. Any idea why?
On the other hand lowering your pullup resistor to 1K should speedup the rise 3 times. That could be sufficient to have a "1" in time. And 1 K isn't too strong, but it would increase the overall power drain if you use RDY frequently.

I'm not sure why there would be such high capacitance at all unless it's to do with the trace length + internal planes?, the trace length between the cpld and the CPU is not very long and this is on a 4 layer board with internal power/gnd planes

Here's a picture of the section of the board. note that while the trace continues above I cut the trace where marked and noticed no difference at all.

I assigned the RDY output of the CPLD to an unused pin to isolate whether there's some capacitance caused by the cpu or anything like that and even then same deal
Results with a 1K resistor below

Well it looks a little better using 1K. Still your capacitance there seems to be unusually high. That short track between your CPLD and the CPU won't be the reason. Does the track runs further or is that red cross above pin 2 a cut?

You synthesize your signal relative to "rising_edge(PHI2)". This is very late as RDY is sampled with the falling edge of PHI2. You could win 100 ns if you release RDY into high Z at the falling_edge(PHI2).

Did you record the signal with inserted CPU or w/o ? The processor contains an "active pullup" which should help significantly.

In POC V2, I arranged so the CPLD would drive RDY high after the wait-state period had expired. Following that clock cycle, the CPLD goes to hi-Z, leaving only the 3.3K pullup resistor to hold RDY high.

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Not necessarily. WDC's MPUs no longer have the internal pullup.

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I cut the track where the red cross is to isolate it but it didn't make a difference

This is both with/without the CPU inserted. as above I even assigned the RDY output to an unused pin of the CPLD and connected it only to a 3k3 pull-up resistor but the waveform was the same.

This might be what I need to do, still I'm surprised at rise time and cannot understand why it's behaving like this. maybe a faulty CPLD? It's a TQFP part so I'm not exactly about to pull it off and replace it with another but I might breadboard another one to test I guess.

Most likely the oscilloscope probe adds this mysterious large capacitance! Sorry, I didn't consider that.

Nevertheless, BDDs solution driving the pin for just one cycle (or even only 1/2 cycle) sounds very well. Then you may choose even a larger pullup R to save some current.

There's often a compensation set screw on a 'scope probe which you can adjust to null out the probe's own capacitance.
https://www.tiepie.com/en/fut/probe#Compensation

I believe/assume LIV2 uses a 1:1 probe which would add pretty much C to this signal. Using 10:1 setting would most likely show there is no trouble at all

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*facepalm* you were right! much better at 10x

The system still doesn't work properly unless I drive the signal high rather than high-z but I'm glad to have figured out what was so wrong with the slow rise-time

Options mentioned above by you all are
1: use a 1k resistor
2: Change the flip-flop clock from rising to falling edge of PHI2
3: BDD's method of driving the signal high before going high-z

Unfortunately the resistor is so close to an ic socket I'd probably make a mess trying to remove it so I'll see what I can achieve with options 2&3

You don't necessarily need to remove the resistor. Instead, can you just leave it in place and add another resistor in parallel? It's alright if the combined value is less than 1K; this will aid the cause. Without having seen the specs for your CPLD I'm guessing you could go down to a few hundred ohms or even less. The extra current consumption is probably unimportant (unless it's a battery-powered application).

I have some doubts about options 2&3. Unless I'm missing something the flip-flop is intended to produce a wait state (IOW pause the CPU) in response to certain addresses on the bus (such as addresses mapped to a slow ROM). The decision regarding the need for a wait-state is one that needs to be made partway through the cycle. The rising edge of Phi2 is an acceptable time because it satisfies two requirements: it's late enough for the address to be valid (so we know if it's ROM or not) and also early enough to allow the CPU sufficient setup time before it samples the RDY signal (at the fall of Phi2).

Option 3 (driving the signal high before going high-z) involves a tradeoff, as there's the risk of a WAI instruction trying to simultaneously drive RDY low. The risk may not be much to worry about, but using an unaided pullup resistor eliminates the risk entirely, and to me seems a simpler solution. (As noted, the pullup needs to have a suitably low resistance.)

-- Jeff

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I think the CPLD should be able to handle it, just wondering how much the CPU can sink on that RDY pin since I recall reading here that a value too low etc could cause the CPU to be unable to pull RDY low and thus continue immediately after a WAI instruction (though I doubt I'll ever use WAI)

I really should've left more space or mounted the resistors & caps on the bottom of the board... oh well lesson learnt!