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 Post subject: Re: 65VM02
PostPosted: Mon May 15, 2017 7:46 am 
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I'm glad for what you're doing, Hugh, and I'm anxious to keep reading about your developments. Don't stop. I'm sure you're no threat to Forth, Inc. (or to anyone else, AFAIK). Apparently I miscommunicated something, and I'm not sure what or how. I was just saying Forth today is being used not just by hobbyists, but at a very professional level. I really don't know anything about the company Forth, Inc. other than what's on their website. Their products and services appear to be very impressive, but I've never done business with them to have an opinion about them as a company. I might be interested in your experience with them, although it will be for intellectual and historical interest, not anything personal, since they're in a much higher league than I care to be in. If you think it's not appropriate to post here (or in the Forth section of the forum), you can PM or email me.

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 Post subject: Re: 65VM02
PostPosted: Mon May 15, 2017 9:12 am 
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There does seem to have been a bit of culture change on this forum in the last month or two. Both regulars and newcomers seem to be happy to make challenging statements of opinion as if they are spoiling for an argument. That's not usually how we proceed here, although we've had our share of disagreement.

It helps, I think, to qualify claims as being your own thoughts or opinions. (When I say "you" or "yours" I mean anyone here.)

It doesn't help to take a position that some technology or product is dead, or not viable, or uninteresting. Any one of us might have such an opinion, but stating that kind of opinion doesn't allow for any kind of illuminating or productive discussion.

Especially claims that something is uninteresting, or not useful, or incomprehensible - those are negative claims which simply don't belong. The forum is not here for such a narrow purpose that all of us can find every subject interesting. If you don't like a topic, just don't follow that topic. There are plenty of others. If you'd like to understand something, but don't yet understand it, by all means try to gain understanding through discussion.


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 Post subject: Re: 65VM02
PostPosted: Mon May 15, 2017 9:27 pm 
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Tor wrote:
Hugh Aguilar wrote:
GARTHWILSON wrote:
Quote:
the same is true of Forth programming --- no jobs; it is just a hobby.

Forth, Inc. might have a different view. Forth is their bread & butter.

You seem to be very concerned that my 65VM02 will steal the bread and butter from Forth Inc.'s table.

This is your forum. If you want to support Forth Inc., then just say so and I will never post another message on your forum again. You do what you think is best.
? That's not what Garth meant at all (as he'll comment when his timezone comes around again) - your 65VM02 is extremely welcome on this forum.

Well, just be aware that Forth Inc. will do everything in their power to discredit the 65VM02 or any other Forth that anybody comes out with. The whole purpose of Forth Inc. writing the ANS-Forth standard in 1994 was so they could say that the competition is just a non-standard wanna-bee. It is not a coincidence that my MFX was written in 1994/1995 and that I wrote MFX in UR/Forth, and that MFX and UR/Forth were both discredited by ANS-Forth as being non-standard and instantly obsolete. Also, be aware that Forth Inc. tried to get that job at Testra writing the development system for the MiniForth processor. Testra hired me instead, and Forth Inc. has never forgiven me for stealing the bread and butter from Forth Inc.'s table. Elizabeth Rather said (on the Forth-200x mailing-list) that I got fired from Testra because the MFX was no good. That is a lie --- Testra continues to use MFX today (their RACE is just the MiniForth upgraded from the Lattice isp1048 PLD to an FPGA).

Anyway, I have a new update on the 65VM02 design. I got rid of the VIRQ which was over-complicated, and I now have a simpler and better design. I also figured out a way to significantly speed up ENTER and LEAVE which should speed up all code that uses local variables. What I have now is, I think, as efficient as is reasonably possible --- there is no further opportunity for new instructions that do things in parallel internally.


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File comment: I got rid of VIRQ and replaced it with AIRQ, and I also sped up the ENTER and LEAVE code.
65VM02.txt [23.79 KiB]
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 Post subject: Re: 65VM02
PostPosted: Mon May 15, 2017 9:43 pm 
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Rob Finch wrote:
If a goal is to be a byte-code interpreter engine I think a 128kB design would be somewhat limiting. I think if it was possible to use a 24 bit address space that would be good. This would mainly affect the IP instructions. Several small JVM’s are larger than 128kB. Of course this might mean supporting a long address mode (‘C816 compatible).

I have no intention of supporting JVM --- Java isn't my cup of tea --- also, Java is 32-bit, so I think it needs a 32-bit processor.

The 65VM02 is for applications that are bigger than the typical 8-bit processor program with 128 bytes of memory --- but are not as big as what you would use the STM8 for --- not too small, and not too big.

Note that I previously described 8-bit processor programs with 128 bytes of memory as being "uninteresting" --- I wasn't being disparaging, as this is a worthwhile business (most micro-controllers are in this category and that is where most of the money is) --- I just meant that it is uninteresting to me because it has nothing to do with the 65VM02 design.


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 Post subject: Re: 65VM02
PostPosted: Mon May 15, 2017 9:50 pm 
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BigDumbDinosaur wrote:
For an increment or decrement to tamper with carry would automatically make your design 6502-incompatible in my world.

Yes, I know that.

The 65VM02 is fully 65c02 compatible and should run all legacy code just fine. INC and DEC are the same as before, as are all the 65c02 instructions. I even left in the weird bugs involving the return-address being one off, and the S register being one off --- there is likely legacy code that works around these "features" and would be broken if this was changed.

I just commented that INC and DEC failing to affect the carry-flag seems like a flaw to me. Certainly I had to work-around this in the CMOVE function, which makes the code bloaty and slow. This was my comment in the code:

Code:
; On the 65c02, DEC doesn't set the C-flag (one of the many flaws in the 65c02 design).
; Because of this, we have to LDA TOSHI,X then subtract 1 then STA TOSHI,X again.
; I could fix this flaw in the 65VM02, but that might break legacy code.


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 Post subject: Re: 65VM02
PostPosted: Mon May 15, 2017 10:18 pm 
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GARTHWILSON wrote:
I was just saying Forth today is being used not just by hobbyists, but at a very professional level. I really don't know anything about the company Forth, Inc. other than what's on their website. Their products and services appear to be very impressive... they're in a much higher league than I care to be in.

Well, don't be over-impressed by a website. The internet is full of websites that appear to represent "very professional" companies that are in a "higher league" than everybody else. :wink:

Only once has anybody shown up on comp.lang.forth claiming to have written a commercial program in SwiftForth. This was Roger Levy and this was the program:
http://store.steampowered.com/app/341060/The_Lady/
If this is a higher league, I think I'll stick to the lower leagues...


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 Post subject: Re: 65VM02
PostPosted: Mon May 15, 2017 10:23 pm 
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I hope I'm not repeating something that was answered elsewhere. I wasn't able to find it if it was. Would you prefer that INC and DEC affect the carry flag, while INY, DEY, INX, and DEX do not? INX, DEX, INY, and DEY are often used for loop counting, and the top of the loop needs the C result from the bottom from just before the DEY for example, as shown in the multiply routines at viewtopic.php?p=4389#p4389 starting with Bruce's post.

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 Post subject: Re: 65VM02
PostPosted: Tue May 16, 2017 2:53 am 
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GARTHWILSON wrote:
I hope I'm not repeating something that was answered elsewhere. I wasn't able to find it if it was. Would you prefer that INC and DEC affect the carry flag, while INY, DEY, INX, and DEX do not? INX, DEX, INY, and DEY are often used for loop counting, and the top of the loop needs the C result from the bottom from just before the DEY for example, as shown in the multiply routines at viewtopic.php?p=4389#p4389 starting with Bruce's post.

I added these to the 65VM02:
Code:
ADY #value          add the value to Y, setting the N Z V and C flags (in the same way as ADC does)
SBY #value          subtract the value from Y, setting the N Z V and C flags (in the same way as SBC does)

So, I've got Y covered, while still leaving DEY and INY as they were. I don't have anything like DEC and INC that affects the C-flag though, which is why I had to work around that problem in the CMOVE primitive. I suppose I could provide new instructions there too, but I don't want to add too many new instructions, and this is a minor issue.

As for DEX and INX I just use X for the data-stack pointer so it never rolls over, so these are fine as they are.


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 Post subject: Re: 65VM02
PostPosted: Wed May 17, 2017 6:20 pm 
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I don't really know very much about multi-tasking OS design. I've never used one --- it is just something I've read about, and not very much.

Previously I had the T flag and I assumed that there could not be a task-switch in the middle of a primitive, but a task-switch could only occur in NEXT which is between primitives.

Then I got rid of the T flag. My thought was that only ISRs would access I/O ports, and they would send or receive the data to or from the tasks in circular buffers. It is okay for an interrupt to occur in the middle of a primitive even if the primitive is accessing a circular buffer and the ISR accesses the same circular buffer. So, no worries!

It may be necessary to reintroduce the T flag though, and have it set by the heartbeat timer and checked in NEXT, and make the rule that there can be no task-switch in the middle of a primitive, but only in NEXT. This way a primitive would effectively exclude any other task from accessing the same datum that it is accessing.

Can anybody recommend anything that I could read on the subject of multi-tasking OS design? :?: This is a subject that I need to learn more about before I get further into the 65VM02 design. :?


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 Post subject: Re: 65VM02
PostPosted: Wed May 17, 2017 7:30 pm 
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Hugh Aguilar wrote:
Then I got rid of the T flag. My thought was that only ISRs would access I/O ports, and they would send or receive the data to or from the tasks in circular buffers. It is okay for an interrupt to occur in the middle of a primitive even if the primitive is accessing a circular buffer and the ISR accesses the same circular buffer. So, no worries!

I would just encourage that non-queued things in the I/O still be accessible. Countless times in my applications (in fact it's the most common case), I need to read an input bit or set or clear an output bit in realtime, not waiting on a queue.

Quote:
Can anybody recommend anything that I could read on the subject of multi-tasking OS design? :?: This is a subject that I need to learn more about before I get further into the 65VM02 design. :?


These are from the software section of my links page. There are 13 more there, mostly in the easily spotted indented part of that section, but I have not checked them for which ones have any multitasking involved.

Section 18 of my stacks treatise has some musings and more links on stack usage in multitasking.

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 Post subject: Re: 65VM02
PostPosted: Wed May 17, 2017 8:28 pm 
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Hugh Aguilar wrote:
I don't really know very much about multi-tasking OS design. I've never used one --- it is just something I've read about, and not very much...Can anybody recommend anything that I could read on the subject of multi-tasking OS design? :?: This is a subject that I need to learn more about before I get further into the 65VM02 design. :?

Maurice Bach's Design of the UNIX Operating System is the classic tome on the subject. I purchased my copy in 1987 and have read it cover-to-cover several times. The book does not focus on any one machine architecture, which means you'll get a more balance view of the theory behind a proven preemptive, multitasking design.

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 Post subject: Re: 65VM02
PostPosted: Wed May 17, 2017 8:43 pm 
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I'd go for Tanenbaum! Modern Operating Systems on the one hand, and Operating Systems, Design and Implementation on the other.


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 Post subject: Re: 65VM02
PostPosted: Thu May 18, 2017 4:08 am 
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GARTHWILSON wrote:
Hugh Aguilar wrote:
Then I got rid of the T flag. My thought was that only ISRs would access I/O ports, and they would send or receive the data to or from the tasks in circular buffers. It is okay for an interrupt to occur in the middle of a primitive even if the primitive is accessing a circular buffer and the ISR accesses the same circular buffer. So, no worries!

I would just encourage that non-queued things in the I/O still be accessible. Countless times in my applications (in fact it's the most common case), I need to read an input bit or set or clear an output bit in realtime, not waiting on a queue.

At one time I had this instruction:
Code:
EXA adr         exchange A with an 8-bit variable (at an absolute address, not a direct-page address)

The purpose of this was to read and write a semaphore in a single instruction so it couldn't be interrupted in the middle (this works with an absolute address rather than a direct-page address because the direct-page is task-specific).

I may go back to EXA so I can have a primitive that reads and writes a semaphore and can't be interrupted. This would allow code such as you are describing (accessing an I/O port from a task and being sure that you don't get a task-switch in the middle of accessing the port) --- and this code could be written in Forth.

I still don't like the idea of a task-switch being only on NEXT because this slows down NEXT --- also, this means that accessing an I/O port has to be done inside of a primitive, which means that it has to be written in assembly-language --- it is much more convenient if this could be written in Forth using C@ C! etc., but this involves multiple primitives.

Thanks for the links to information on multi-tasking OS design, from you and the others --- I will read up on that. :-)


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 Post subject: Re: 65VM02
PostPosted: Thu May 18, 2017 6:22 am 
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Since you're designing your own versions of the processor, you might be able to make NEXT a machine-language instruction, and have, in hardware, something like the cam on WWI planes' machine guns that allowed them to shoot through the propeller without shooting it off. :lol: The signal to switch tasks, or other interrupt, is only accepted at certain times. A lot of overhead disappears if interrupts and task switches only happen at NEXT. The input could alter the behavior of NEXT. This way, there's no slowing of NEXT, at least most of the times it runs. It might be good to look at how Jeff Laughton did his in his KimKlone 6502 w/ pointer-arithmetic-friendly extended address space and 9-cycle ITC Forth NEXT. In fact, he has quite a knack for taking an existing processor and improving it a lot without starting over. This can be done in programmable logic much more easily than doing the whole processor design.

In my 0-overhead Forth interrupts method (ITC) on the '02, NEXT normally takes three more clocks than the non-interrupt-equipped NEXT, slowing normal overall execution down less than 4%. However, when an interrupt does hit, my NEXT is actually quite a bit faster than the normal, because we no longer have to increment the Instruction Pointer when going to the interrupt-handling word. If we did, the latter would be replacing the next Forth instruction in the main code instead of delaying it. In that sense, the overhead is actually negative (would that be "underhead" instead of "overhead"?) when going to an ISR.

My ITC '816 Forth's NEXT works a little differently, with self-modifying code, and JMP NEXT at the end of primitives is replaced with JMP (NEXTadr) to get to the right version of NEXT for the conditions. This would also let you put into NEXTadr the address of later-added versions of NEXT, like a program-trace version (although I found that such a trace is never needed in Forth), and swap addresses out on the fly. The indirection adds three clocks, but removes the conditional branch from the normal version of NEXT. [Edit, 5/20/17: Jeff Laughton was reminding me that there's a way to use additional self-modifying code to do the job on the '816 with zero added cycles for the non-interrupt situation. It adds five cycles in the interrupt situation.]

Perhaps you're thinking of something I'm forgetting; but C@ (whether I/O byte or otherwise) is not like @ which can get interrupted between the fetch of the two bytes if it's on an '02 and not the '816. C@ and C! shouldn't cause any problems even on the '02. OTOH, a primitive that does a R-M-W on a single byte but without the benefit of being able to do it in a single instruction like INC or TSB may require care. What I do (in assembly language too) when reading the RTC bytes in memory that get incremented by a timer interrupt is to read them multiple times until I get the same thing twice in a row, eliminating the possibility of invalid sets when the low byte's rollover carries into higher bytes in the middle of the reading process.

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 Post subject: Re: 65VM02
PostPosted: Thu May 18, 2017 7:44 am 
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You could make different interrupt priorities, where the highest priority would be handled in assembly language, and can happen at any time, and a lower priority one that works on Forth level, and can only happen during NEXT.


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