Hi

I have this project in which I want to interface a 6502 to a lattice CPLD and while is sounds quite straight-forward, its not quite so simple.

I have tested different ways of doing it, and as the CPLD wants to have a common clock (which I set as its internal FPGA clock at 133MHz), there is some twists in order to get it smoothly compiled into a real device.

The simulator (Lattice Diamond) seems to be able to do most things, while the real world is somewhat different (but you all know how that is).

What I WANT to do is to make an internal clock that is set at about the same frequency as the external 6502, then reset the internal Clock with basis of the external CLK2 signal (the Clock is constructed by a counter from the FPGA clock edge). This seems to work fine in the simulator, but not so within the CPLD. I am unable to get the two clocks syncronized, which is probably not so surprising given my short experience with CPLDs.

What I am able to do is by using the WR signal from the 6502 and write to the CPLD memory. I can also use the address lines to trigger the writing/reading, but using the external CLK2 is not working.

Basically, the logic to synchronize an internal clock with an external is what I would like to get going. So my question to you is how you would go about this to get clock synchronization. Or maybe I am just thinking of this the wrong way, so what solution would you use to get an internal clock and external clock to work together? I want to keep the 133MHz clock for fast internal logic (basically I trigger memory read/write with it, so I can have the memory interface to other things most of the time).

I know I can just skip the clock thing and go directly with the address signals and it would work, but this is one of those problems that is just too irritating to put on a shelf. I would really like to see if there is a good solution to it.

Rather than trying to synchronise two clocks, as you have a master clock which is a great deal faster than the 6502 clock, may you can just sample the 6502 clock the same way you sample the RnW and address lines.

For a 6502 write, CPLD read, when your state machine sees the clock going from high to low, you know that the previous sample was the final sample during that Phi2.

For a 6502 read, CPLD write, you need to sample the address lines and start driving the bus some little time before the end of Phi2. Either you can count from the last falling edge, knowing the frequencies, or again you can sample Phi2 and choose to drive only in the second half of the cycle.

Easy solution to keep the clocks synchronized is to have the CPLD generate the 6502 clock by a divider. But that only works if you can control the 6502's clock. If you're trying to attach to existing hardware, I would follow BigEd's advise. Make sure you use a synchronizer (two registers in a row) to capture the clock.

That would probably work. Just disregard the CLK2 as a clock and check its state instead. Why didn't I think of that!


The 6502 is uncontrolled, so I have to follow it somehow. But I have been so narrowminded with respect of treating the CLK2 as a clock that I ended up making an internal CLK2-clock just to keep it that way.

You can synchronize the external clock to the internal one by a series of synchronisation registers (as mentioned by others), but check your CPLD documentation for the metastability figures so you know how many registers is 'officially' enough. And take the syncrhonisation delay into account when doing things that involve both clocks.

If you have PLLs in there (but in most CPLDs you don't), another solution would be to use the external clock as the reference clock going into the PLL. Given some thoughtful parameterisation of the PLL, that would effectively synchronize the clocks as well.

I finally managed to get it going with an internal clock and using the address lines for syncronization:



The Vic-20 shown above is the digitized output from a real one:



Currently it only acts as a memory expansion using the internal EBR Ram of the CPLD. My next step is to add a 6502 core of some kind.