Hi
I have this project in which I want to interface a 6502 to a lattice CPLD and while is sounds quite straight-forward, its not quite so simple.
I have tested different ways of doing it, and as the CPLD wants to have a common clock (which I set as its internal FPGA clock at 133MHz), there is some twists in order to get it smoothly compiled into a real device.
The simulator (Lattice Diamond) seems to be able to do most things, while the real world is somewhat different (but you all know how that is).
What I WANT to do is to make an internal clock that is set at about the same frequency as the external 6502, then reset the internal Clock with basis of the external CLK2 signal (the Clock is constructed by a counter from the FPGA clock edge). This seems to work fine in the simulator, but not so within the CPLD. I am unable to get the two clocks syncronized, which is probably not so surprising given my short experience with CPLDs.
What I am able to do is by using the WR signal from the 6502 and write to the CPLD memory. I can also use the address lines to trigger the writing/reading, but using the external CLK2 is not working.
Basically, the logic to synchronize an internal clock with an external is what I would like to get going. So my question to you is how you would go about this to get clock synchronization. Or maybe I am just thinking of this the wrong way, so what solution would you use to get an internal clock and external clock to work together? I want to keep the 133MHz clock for fast internal logic (basically I trigger memory read/write with it, so I can have the memory interface to other things most of the time).
I know I can just skip the clock thing and go directly with the address signals and it would work, but this is one of those problems that is just too irritating to put on a shelf. I would really like to see if there is a good solution to it.