Elsewhere on the forum there's a note about the lack of CUPL tutorials, so I though start things off I'd mention some code I've been using that makes CUPL files easier to read, and reduce the chances of typos.
It's quite common to see CUPL files that rely on testing individual address bits to do chip selection and the like. With equations like:
Code:
!ramcs = !A15 ;
!io = !A13 & !A14 & A15 ;
!romcs = A13 & A14 & A15 ;
It's not exactly clear from the equations what the memory map is
WinCUPL has the "FIELD" definition to make thing easier to read (and reduce typo issues).
With just pins A13 to A15 defined you can still use:
Code:
FIELD address = [A15..A0] ;
!ramcs = address:[0000..7FFF] ;
!io= = address:[8000..AFFF] ;
!romcs = address:[E000..FFFF] ;
The compiler will let you know if the address range can't be achieved with the declared pins.
The GAL code below was for a test board that had 32k ram, 16k rom, a ZXspectrum style 6k+ 3/4k attributes screen map and 4 I/O decodes. The field definition almost makes the memory map at the bottom redundant.
Code:
Name 6502test ;
PartNo 00 ;
Date 09/02/2018 ;
Revision 01 ;
Designer Engineer ;
Company None ;
Assembly None ;
Location ;
Device p22v10 ;
/* *************** INPUT PINS *********************/
PIN 1 = A12 ; /* 6502 address lines */
PIN 2 = A13 ; /* Order skewed to match wiring */
PIN 3 = A14 ; /* */
PIN 4 = A15 ; /* */
PIN 5 = A11 ; /* */
PIN 6 = A10 ; /* */
PIN 7 = A9 ; /* */
PIN 8 = rw ; /* VGA board accesses memory */
PIN 9 = phi2 ; /* on phi low */
pin 10 = A8 ; /* */
pin 11 = A7 ; /* */
pin 13 = A6 ; /* */
/* *************** OUTPUT PINS *********************/
PIN 14 = wr ; /* qualified read and write */
PIN 15 = rd ; /* to avoid contention with VGA */
PIN 16 = colour ; /* video memory split over */
PIN 17 = screen ; /* 2 devices */
PIN 18 = io6 ; /* 4 I/O blocks */
PIN 19 = io4 ; /* */
PIN 20 = io2 ; /* */
PIN 21 = io0 ; /* */
PIN 22 = ramcs ; /* main memory chip selects */
PIN 23 = romcs ; /* */
Field address = [A15..0];
/* 32k main memory */
!ramcs =
address:[0000..7FFF]
;
/* The VGA CPLD expects the first 6k of the 8k space allocated for the bitmap */
!screen =
address:[8000..97FF]
;
/* The VGA CPLD expects the next 768 bytes to be allocated for the colour memory */
!colour =
address:[9800..9AFF]
;
/* I/O allocated in the otherwise un-used 1.25k in the 8000 to 9FFF block */
/* since there is room to decode additional addres lines on the GAL the I/O areas are only 64 bytes */
/* making 9C00 to 9FFF available for additional hardware which will need decoding by the expansion */
!io0 =
address:[9B00..9B3F]
;
!io2 =
address:[9B40..9B7F]
;
!io4 =
address:[9B80..9BBF]
;
!io6 =
address:[9BC0..9BFF]
;
/* 24k ROM available to fill the remainder of the map - currently set for 16k only */
/* !romcs = address:[A000..FFFF] ; */
!romcs =
address:[C000..FFFF]
;
/* databus only valid while PHI is high so read and write are both qualified */
!rd = rw & phi2 ;
!wr = !rw & phi2 ;
/* Memory map */
/* 0000 - 7FFF 32k RAM */
/* 8000 - 97FF 6k Screen bitmap */
/* 9800 - 9AFF 0.75k Screen colours */
/* 9B00 - 9B3F 64 Byte I/O block 0 */
/* 9B40 - 9B7F 64 Byte I/O block 1 */
/* 9B80 - 9BBF 64 Byte I/O block 2 */
/* 9BC0 - 9BFF 64 Byte I/O block 3 */
/* 9C00 - 9FFF 1k expansion I/O */
/* A000 - FFFF 24k ROM */
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. However, I used an ATF22V10CQZ on my last SBC. Peter (cbscpe here) showed simplified WinCUPL detail for the Glue logic I was working on (using the FIELD statement). It obviously made more sense for defining address ranges for the RAM, ROM and I/O addresses. I also used the single glue chip to generate phase 2 clock validated memory read/write signals.
