Ok, I might be just seeing the wood for the trees, but I cannot see why I'm getting a CSIM error complaining about the parameters in the .SI file.
Would anyone be willing to cast a fresh set of eyes over this for me?
This is the code:
Code:
Name AddressDecoder1;
Partno Lattice22V10B;
Date 11/07/15;
Revision 01;
Designer shalewyn.com;
Company shalewyn.com;
Assembly 1;
Location 1;
Device g22v10;
/*
* Lattice GAL 22V10B pinout, DIP, top view
*
* I/CLK.[ 1 24 ].VCC
* I.[ 2 23 ].I/O/Q
* I.[ 3 22 ].I/O/Q
* I.[ 4 21 ].I/O/Q
* I.[ 5 20 ].I/O/Q
* I.[ 6 19 ].I/O/Q
* I [ 7 18 ].I/O/Q
* I [ 8 17 ].I/O/Q
* I [ 9 16 ].I/O/Q
* I [ 10 15 ].I/O/Q
* I [ 11 14 ].I/O/Q
* GND.[ 12 13 ].I
*
*/
/*
* Inputs
*/
Pin 1 = phi2;
Pin 2 = cpuRW;
Pin [3..10] = [A15..8];
/*
* Outputs
*/
Pin [16..23] = [S0..7];
/*
Pin [16] = s[0]; nROM select;
Pin [17] = s[1]; nRAM select;
Pin [18] = s[2]; nLatch1 select;
Pin [19] = s[3]; nVIA #1
Pin [20] = s[4]; nVIA #2
Pin [21] = s[5]; nACIA
Pin [22] = s[6]; nWR;
Pin [23] = s[7]; nRD;
*/
/*
* Main
*/
FIELD AddressBus = [A15..8];
FIELD Selects = [S7..0];
/* Note that each device which can be written to has 2 entries - one for reading and
* one for writing. This is because writing should only ever happen when phi2 is HI
* so we need one rule which allows read if cpuRW is HI and one rule which only
* allows writes when cpuRW is LOW and phi2 is HI.
* ADDENDUM: I've chnaged this so that both read & write need phi2 to be high. This is
* to make it compatible with the 65C816. */
TABLE AddressBus => Selects {
[0000..1FFF] => 'b'01000001 & cpuRW & phi2; /* Non-swap RAM read */
[0000..1FFF] => 'b'01000010 & !cpuRW & phi2; /* Non-swap RAM write */
[2000..7FFF] => 'b'01000001 & cpuRW & phi2; /* Swap RAM read */
[2000..7FFF] => 'b'01000010 & !cpuRW & phi2; /* Swap RAM write */
[8100..810F] => 'b'00010001 & cpuRW; /* VIA #1 read */
[8100..810F] => 'b'00010010 & !cpuRW; /* VIA #1 write */
[8200..820F] => 'b'00001001 & cpuRW; /* VIA #2 read */
[8200..820F] => 'b'00001010 & !cpuRW; /* VIA #2 write */
[8300..830F] => 'b'00000101 & cpuRW; /* ACIA read */
[8300..830F] => 'b'00000110 & !cpuRW; /* ACIA write */
[9000..FFFF] => 'b'10000001 & phi2; /* ROM read*/
}
Partno Lattice22V10B;
Date 11/07/15;
Revision 01;
Designer shalewyn.com;
Company shalewyn.com;
Assembly 1;
Location 1;
Device g22v10;
/*
* Lattice GAL 22V10B pinout, DIP, top view
*
* I/CLK.[ 1 24 ].VCC
* I.[ 2 23 ].I/O/Q
* I.[ 3 22 ].I/O/Q
* I.[ 4 21 ].I/O/Q
* I.[ 5 20 ].I/O/Q
* I.[ 6 19 ].I/O/Q
* I [ 7 18 ].I/O/Q
* I [ 8 17 ].I/O/Q
* I [ 9 16 ].I/O/Q
* I [ 10 15 ].I/O/Q
* I [ 11 14 ].I/O/Q
* GND.[ 12 13 ].I
*
*/
/*
* Inputs
*/
Pin 1 = phi2;
Pin 2 = cpuRW;
Pin [3..10] = [A15..8];
/*
* Outputs
*/
Pin [16..23] = [S0..7];
/*
Pin [16] = s[0]; nROM select;
Pin [17] = s[1]; nRAM select;
Pin [18] = s[2]; nLatch1 select;
Pin [19] = s[3]; nVIA #1
Pin [20] = s[4]; nVIA #2
Pin [21] = s[5]; nACIA
Pin [22] = s[6]; nWR;
Pin [23] = s[7]; nRD;
*/
/*
* Main
*/
FIELD AddressBus = [A15..8];
FIELD Selects = [S7..0];
/* Note that each device which can be written to has 2 entries - one for reading and
* one for writing. This is because writing should only ever happen when phi2 is HI
* so we need one rule which allows read if cpuRW is HI and one rule which only
* allows writes when cpuRW is LOW and phi2 is HI.
* ADDENDUM: I've chnaged this so that both read & write need phi2 to be high. This is
* to make it compatible with the 65C816. */
TABLE AddressBus => Selects {
[0000..1FFF] => 'b'01000001 & cpuRW & phi2; /* Non-swap RAM read */
[0000..1FFF] => 'b'01000010 & !cpuRW & phi2; /* Non-swap RAM write */
[2000..7FFF] => 'b'01000001 & cpuRW & phi2; /* Swap RAM read */
[2000..7FFF] => 'b'01000010 & !cpuRW & phi2; /* Swap RAM write */
[8100..810F] => 'b'00010001 & cpuRW; /* VIA #1 read */
[8100..810F] => 'b'00010010 & !cpuRW; /* VIA #1 write */
[8200..820F] => 'b'00001001 & cpuRW; /* VIA #2 read */
[8200..820F] => 'b'00001010 & !cpuRW; /* VIA #2 write */
[8300..830F] => 'b'00000101 & cpuRW; /* ACIA read */
[8300..830F] => 'b'00000110 & !cpuRW; /* ACIA write */
[9000..FFFF] => 'b'10000001 & phi2; /* ROM read*/
}
This is the SI file:
Code:
Name AddressDecoder1;
PartNo Lattice22V10B;
Date 11/07/15;
Revision 01;
Designer shalewyn.com;
Company shalewyn.com;
Assembly 1;
Location 1;
Device g22v10;
ORDER: phi2, cpuRW, A15..A8, S0, S1, S2, S3, S4, S5, S6, S7;
VECTORS:
/* each test comprises of a set of read and a set of writes.
* 1st test is for PHI2 being HI and the 2nd for PHI being LOW */
/* Base RAM test 2xRead, 2xW1rite */
1 1 '1000' ********
1 1 '3000' ********
1 1 '8100' ********
1 1 'A000' ********
PartNo Lattice22V10B;
Date 11/07/15;
Revision 01;
Designer shalewyn.com;
Company shalewyn.com;
Assembly 1;
Location 1;
Device g22v10;
ORDER: phi2, cpuRW, A15..A8, S0, S1, S2, S3, S4, S5, S6, S7;
VECTORS:
/* each test comprises of a set of read and a set of writes.
* 1st test is for PHI2 being HI and the 2nd for PHI being LOW */
/* Base RAM test 2xRead, 2xW1rite */
1 1 '1000' ********
1 1 '3000' ********
1 1 '8100' ********
1 1 'A000' ********
The error that I'm getting:
Attachment:
wincupl_error.jpg [ 17.79 KiB | Viewed 5077 times ]
The SO file is giving me '[0014sa] insufficient test values', but I cannot see where i'm goign wrong on the SI file. I've tried inserting a BASE=HEX statement, but this doesn't help.
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