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 Post subject: Re: M65C02A Core
PostPosted: Mon Mar 14, 2022 7:46 pm 
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Joined: Sun Jun 30, 2013 10:26 pm
Posts: 1927
Location: Sacramento, CA, USA
It might be a whimsical notion occurring too late in the game, but a complement-and-add with carry (CDC) or negate-and-add (NDD) instruction would obviate the need to swap arguments in some cases. I have plenty of opcode slots in my 65m32, so it will definitely have at least one of those before it's ready for prime-time. "Whimsical" and "late" are integral parts of my personal mantra.

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Mike B. (about me) (learning how to github)


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 Post subject: Re: M65C02A Core
PostPosted: Mon Mar 14, 2022 9:57 pm 
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Joined: Mon Apr 23, 2012 12:28 am
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Location: Huntsville, AL
When programming in assembly language, or perhaps using a non-recursive descent compiler without too much intelligence, it's fairly easy to set up the evaluation order of the operands for instructions like CMP and SUB/SBC where operand order is important. On the other hand, having done only a minimal amount of 8086 assembly language programming, I was surprised at how flexible some of the instructions are with respect to operand order.

So it's not a whimsical notion to contemplate about being able to support reverse operand order in your instruction set. The simple accumulator / memory architecture of the 6502/65C02 makes it difficult to easily swap operand order for instructions when it matters. A three register instruction set architecture makes it much easier to control operand order.

As always, Mike, I enjoy hearing from you. I would never have thought of naming the instructions in the manner you suggested. I just don't think that way. :D

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