The trouble with propagation delay is, it's not predictable or well specified. No minimum figure, as Garth said.
A better way -- and the normal and natural way -- to implement a delay with programmable logic is via a counter. At the start of the delay the counter would be loaded, then it would proceed to decrement (or increment) according to a clock signal that's been chosen as a time base. The delay is complete when the counter reaches its terminal value (typically zero if you're decrementing).
That same basic idea can work for you, too. Presumably this 6526 device -- a 65xx peripheral -- gets the Phase 2 signal fed to it, and that can serve as your time base. From the datasheet you posted, I see the delay commences with a write to PRB. This would load your counter, which would subsequently decrement at the Phase 2 rate until the delay is complete. You'd arrange for CB to be low anytime the counter is not at its terminal value. This gives a nicely defined pulse following a write to PRB.
You'd need to decide whether the counter decrements on the rising or falling edge of Phase 2, and what the initial count should be. Looks like that count might be be extremely small -- like, 1! A simple flipflop might serve as the "counter." It would "count" from 1 down to zero. Possibly the original 6526 logic is just as I describe.
-- Jeff