Another idea for the list, yes! First up would be the addition of the conventional opcodes for the C02 - the push and pull of X and Y, INC A and DEC A, the indirect zero page operations, BRA, JMP indexed indirect and so on.

I've said before that there are useful aspects of the 816 to be brought into play, to offer 24-bit addresses for data access, without tackling the enormous task of a full 816 core. Unfortunately, columns 7 and F contain some of those useful opcodes in the 816, and contain the zero-page bit-mode instructions in the 65C02. So that's two competing models...

What probably should apply here, though, is to step back from cycle counts and consider real elapsed time. Any FPGA CPU can run at 10MHz and up - generally limited by external memory speed, if there is external memory. So for bit-banged peripherals, as for interrupt latency, our level of anxiety about using extra cycles should be reduced by at least a factor of ten.

(It's also true that a fast FPGA CPU can output the system clock and do its own address decoding and clock-stretching to arrange that access to 1MHz peripheral chips is seamless. So long as there are a few free pins.)

Cheers
Ed

(As noted elsewhere, there are already two 65C02 cores in HDL which offer the bitwise instructions:

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