I'm starting to get a feel for this new design and that I'll most likely need more room to route all the pins from the 96-pin connector to the FPGA so I most likely need a wider path to it from the FPGA. The board can be extended vertically, especially since I can tighten the horizontal. So that's what I attempted here, cutting sections apart to save time for an approximate size. New dimensions are 5.5"x3.81". Long day at work, will have to stop there. I expect to make huge gains in the next 2 days off though.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

What's left of my brain is burnt to a crisp. Got alot done tho in 10.5 hrs! Had to resize the board again, it's now 6.4" x 3.25".
Wiring up the SyncRAMs was pretty easy.
I ran into trouble wiring up the HDMI Receiver, it was too close.

Completed:
2 SyncRAMs
3 USB to UART IC's.
3 momentary tactile reset switches.
JTAG connector.
HDMI Receiver and connector.
Internal ground planes for FPGA VCCInt 1.8V and HDMI core 1.2V LDO regulators.

Remaining:
FPGA SPI FLASH PROM connections. Man what a b*tch! What is CSO doing way over on pin AF/4?!!
I2C connections.
I2S audio section wiring.
DS1085L programmable oscillator wiring.
SPI FLASH storage ICs & wiring. The biggest available! >64Mbit?
Micro/mini SD card connector & wiring.
96-pin K9 connector wiring.
Wireless transceiver IC's & wiring.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Just a quick one EE - alot of this is over my head...

Anyway, I trust that wen you do get this board made up you will document the build process? Though a great deal of what you are doing is far ahead of my knowledge - I'm still at the stage of playing about with small CPLDs - I'm really intersted to hear that such boards can be designed, built at a PCB houe for a "reasonable" cost, and assembled without "too mch" special equipment.

Actually that's an assumption; I'm assuming your building this yourself and not having the PCB house do the full build...

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8 bit fun and games: https://www.aslak.net/

My documentation here is the build process. However, the final version will be posted.

I encourage you to post your progress & questions here.

This is correct. I'm attempting to design the board and installing the BGA IC's.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Another change in board dimensions to 7" x 3". Most likely the final change...

15 traces are still shown unused on the top of the board on the right side of the FPGA.

Completed:
2 SyncRAMs
3 USB to UART IC's.
3 momentary tactile reset switches.
JTAG connector.
HDMI Receiver and connector.
Internal ground planes for FPGA VCCInt 1.8V and HDMI core 1.2V LDO regulators.
FPGA SPI FLASH PROM connections. Man what a b*tch! What is CSO doing way over on pin AF/4?!! (Figured that out)
I2C connections.
I2S audio section wiring.
96-pin K9 connector wiring.

Remaining:
DS1085L programmable I2C oscillator wiring.
SPI FLASH data storage ICs & wiring. The biggest available! >64Mbit?
Mini SD card connector & wiring.
Wireless transceiver IC's & wiring.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

EEyE:

If you're looking for a widely supported, multi-vendor SPI Flash package, I would recommend the SOL-16 package. I have recently used this package to purchase and install some 1Gb+ Spansion SPI Flash parts on a board.

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Michael A.

Michael, Thanks you saved me some time, progress is always being made we have to keep our eyes open! I see Digikey has the 16-pin SOIC version of that 1Gbit Spansion FLASH for $8.23US ea...

I was able to add a 2nd DS1085L, there was a GCLK pin available and some real estate available, so that' ll be it for the I2C bus. The interesting detail about the DS1085L, is that if more than 1 are present on the same bus, 1 must be soldered then the active address reprogrammed before the 2nd DS108L is soldered in. I'll have to remember this during assembly time!

Completed:
2 SyncRAMs
3 USB to UART IC's.
3 momentary tactile reset switches.
JTAG connector.
HDMI Receiver and connector.
Internal ground planes for FPGA VCCInt 1.8V and HDMI core 1.2V LDO regulators.
FPGA SPI FLASH PROM connections.
I2C connections.
I2S audio section wiring.
96-pin K9 connector wiring. Expansion connector not available, these pins are NC on K9.
2x DS1085L programmable I2C oscillator wiring.

Remaining:
1Gbit SPI FLASH(s) data storage ICs & wiring.
Mini SD card SPI wiring.
Wireless transceiverwiring.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

There was room for 16 x 1Gbit FLASH IC's. 8 on top + 8 more directly underneath. Maybe I can find a 74154 1x16 MUX tinylogic IC for the CS's. Won't need all at once, but room for expansion is always nice especially when you figure this board is controlling 6 other video boards.
Can possibly fit 4 wireless transceivers in there too...
Done for today.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Hmm, that 1Gbit Spansion FLASH IC looks to have 2 CS's per package. The block diagram looks like they are both separately active, like they have 2 512Mbit dies in one IC.
Now this makes my situation even worse as I would need 32 separate CS's for 16 IC's!

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Ah, a step in the right direction: Micron 1Gb FLASH, slightly more expensive in the same 16-pin SOP, with 1 CS. Now if I could find a 1:16 MUX in a user friendly SMT...

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

I did have to use an external 74HC154 MUX (U39) in order to save FPGA pins for the 16 1Gbit FLASH CS's. I'm totally burnt. Might be errors, but I doubt it...

EDIT: Ugh. I meant Decoder, not MUX. Been awhile, heh.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Again looking through the election of serial FLASHs. I'm starting to like Michael's choice even though it has 2 CS's per IC. Spansion appears to be the only manufacturer (on Digikey) that have a x8 wide serial IC. The datasheet seems lacking though.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

EEyE:

That Spansion part is a stacked die part. It contains two 512Mb parts. Each select activates a separate die. Refer to the datasheet of the 512Mb part for a more detailed description.

There are only a maximum of 4 serial I/O data lines. Digikey is not always careful in setting up their parts selector, and in the case of this part, both dies may not be accessed simultaneously. Also, I've not seen a x8 serial mode defined for serial NOR Flash.

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Michael A.

Michael, thanks for posting, I'm quite ignorant when it comes to SPI FLASH as I've never worked with these devices. So could you (or anyone) entertain a few questions please.
1) The Micron FLASH IC I posted about a few posts ago was listed on DigiKey as a 256Mbx4 (1Gbit). Does the x4 refer to it's capability to have quad I/O? and not it's internal storage arrangement? And...
2) What is the internal storage arrangement standard? Is there even a standard for FLASH memory? Is it safe to assume when using just regular SPI or extended SPI that 8 bits are shifted out for an LSB and another 8 bits for the MSB? It's tough to read these data sheets.

I ask, because I'm trying to choose a device best suited for this 16-bit project. It's nice there at least seems to be a standardized footprint for serial FLASH in SOIC 16.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

EEyE:


I am pretty sure that Digikey has defined the part incorrectly. Internally it is going to be 8-bit cells in pages, sectors, and blocks as you'd expect. The each has a part and manufacturer ID that provides specifics about the internal organization if that makes a difference for the user. Most of these parts conform to a JEDEC serial Flash memory interface. Some may have some custom/proprietary commands, but most respond to a common set of commands. Many of those commands are common from the smallest parts to the largest parts. Most of the newer parts support x1, x2, and x4 read/write ports. All parts start off in the x1 configuration, and the user can command them to switch into the x2 or x4 I/O configuration.

Another common interface configuration issue is the selection of 24-bit (3 bytes) and 32-bit (4 bytes) addressing. Any device greater than 128Mb (16MB) will require more that 3 bytes of address, but those additional bits can be supplied in several ways. We have just opted to use the larger 4 byte address mode rather than using the 3 byte address mode plus explicit management of the other bits.

When supporting the x2 and x4 I/O configuration, some of the pin functions, e.g. nHOLD, are no longer available; I doubt that you'd be particularly interested in that feature.


My eyes rolled back in my head too when I first looked at the datasheet of one of these larger SPI Flash devices. The nice thing is that the interface is very standard, and with some careful attention to the part ID, it's possible for a single driver to support a number of devices and vendors. We just choose parts that have a common page and sector size such 512 words per page and 4KB per sector. Luckily, there are a wide number of devices from several vendors that provide these features.

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Michael A.