All those new (to me) terms are overwhelming, but it’s absolutely fascinating!
yzoer wrote:
I'm using Altera's EPF10k10 (576LE) for my main project and/or EPM7xxx for CPLD's. eBay's great for sourcing them from China.
Btw, make sure you get the 'S' version so you can use JTAG.
-Yvo
You mean the EPF10K10LC84 84-PLCC? That’s one hell of a chip! It is a CPLD, or not? How does the complete tool chain look like?
barrym95838 wrote:
I think that enso is speculating that he may be able to successfully simulate (or is it emulate?) one or more I/O devices in 6502 machine language, at about 33 (8-bit) MIPS.
OK, that’s an original approach, I really didn’t get that.
Quote:
That's on my 'to-do' list as well. If you find any links that are particularly good, could you share them with me, please?
Gladly Mike, I came across this very basic overview to programmable logic.
http://www.barrgroup.com/Embedded-Syste ... able-LogicIt’s not what you asked for, but I found it useful.
This is also very obvious to find, but it’s really massive informative.
http://en.wikipedia.org/wiki/Verilog#Tu ... _resourcesIt’s worth for hours and hours of entertainment, errrm learning.
I must say that Daryl has all his sources on his website and he helped me through the very first steps in ABEL. I’m beginning to understand how it all works more and more. It’s a shame I have to switch to verilog.
At this point, I could achieve the most and quickest with a Xilinx XC95108-7PC84C , it has 69 I/O’s and has a hobby friendly package.
Time will learn...
enso wrote:
What I mean is that a 100MHz 6502 with enough IO ports can just monitor the IO pins connected to the address bus and control pins and respond as if it were a VIA or whatever peripheral chip. At 100MHz the core has many cycles for every 'real' 65C02 cycle.
Yes, Mike already cleared me up. I can only imagine how fast a 100MHz 6502 is.