Greetings all.
I've been trying to get a simple testBench and rom and ram modules working with Arlet's 6502 core.
I'm very much a noob with pl, and know only enough to be dangerous
I have my tb, and rom at least compiled and running with both Iverilog and Xilinx tools (I don't have any FPGA boards yet), and am getting similar, and odd / unexpected results.
Sometimes the instructions are fetched, other times it seems like it's skipping cycles or something.
From what I've read here, it seems that real h.w. SRAMS can be tricky with this core, and maybe simulated ones as well ?
Is there a particular clk delay I should be using ?
I've just been guessing, and have experimented from #1 .. to #10 so far.
I have a cs(chip select) signal on my ram and roms and have experimented with both
an
Code:
always @(posedge clk) begin
if (cs ) begin
tr1 = address & 16'h0FFF ;
$display ("(rom2)cs:%d address:%h tr1:%h data:%h",cs,address,tr1,data);
data = mem[tr1];
end
end
,
and an
Code:
always @* begin
if (cs ) begin
tr1 = address & 16'h0FFF ;
$display ("(rom2)cs:%d address:%h tr1:%h data:%h",cs,address,tr1,data);
data = mem[tr1];
end
end
Here's the whole Rom :
Code:
module rom2(
cs, // chip select
clk, // clock
address, // Address input
data, // Data output from ROM .. input to CPU
transAdd // debuggin of translated address
);
input cs,clk;
input [15:0] address;
output reg [7:0] data;
output [15:0] transAdd;
reg [15:0] tr1;
reg [7:0] mem [0:4096] ;
initial begin
$readmemb("d:\\xilinx\\mike\\rom_data1.txt",mem);
end
always @(posedge clk) begin
data = 8'hz;
if (cs ) begin
tr1 = address & 16'h0FFF ;
$display ("(rom2)cs:%d address:%h tr1:%h data:%h",cs,address,tr1,data);
data = mem[tr1];
end
end
endmodule
Here's my tb :
Code:
`timescale 1s / 1us
module tb1();
reg clk, reset;
wire [15:0] AB;
wire [7:0] DI;
wire [7:0] DO;
wire WE;
reg IRQ,NMI,RDY;
wire [15:0] transAddr;
reg right;
reg [3:0] op;
reg [7:0] AI,BI;
reg CI,BCD;
wire [7:0] OUT;
wire CO,V,Z,N,HC;
wire [8*6-1:0] statename;
wire [5:0] state;
wire [15:0] PC;
wire [7:0] IR;
reg Ram1Reset,Ramz1cs;
reg Rom2cs;
// --- DUTS -----
CPU cpu1( clk, reset, AB, DI, DO, WE, IRQ, NMI, RDY, state,PC,IR);
ALU alu1( clk, op, right, AI, BI, CI, CO, BCD, OUT, V, Z, N, HC, RDY );
rom2 Rom2(Rom2cs,
clk,
AB,
DI,
transAddr
);
RAMZ ramz1(Ramz1cs,
clk,
WE,
Ram1Reset,
AB,
DO,
DI
);
initial begin
$dumpfile( "cpu1.vcd" );
$dumpvars( 0, tb1 );
#1 clk = 0; // initial value of clock
#1 reset = 1; // assert reset (active hi)
#1 RDY = 1; // **** 0 = cpu stopped ***
#100 reset = 0; // De-assert the reset
#1 Rom2cs = 1;
#1 Ramz1cs = 0; // disable ram
#20240 $finish; // Terminate simulation
end
always
#10 clk = ~clk; // Toggle clock every 10 ticks
endmodule
The ram :
Code:
module RAMZ ( input cs,
input clk,
input WE,
input reset,
input [15:0] addr,
input [7:0] din,
output reg [7:0] dout
);
// reg [15:0] RAM [1023:0];
reg [7:0] RAM [255:0];
initial begin
$readmemh("ramz.txt",RAM);
$monitor ("(RAMZ) cs:%h, clk:%h WE:%h, reset:%h addr:%h din:%h dout:%h",cs,clk,WE,reset,addr,din,dout);
end
always @(posedge clk) begin
dout <= 8'hz;
if (cs) begin
if (WE)
RAM[addr] <= din;
else
dout <= RAM[addr];
if (reset)
dout <= 0;
end
end
endmodule
Mike
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