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Wire-wrapping Xilinx FPGAs
http://forum.6502.org/viewtopic.php?f=10&t=2539		 Page 1 of 1
Author:  enso [ Thu Jun 13, 2013 4:01 am ]
Post subject:  Wire-wrapping Xilinx FPGAs
Life is funny. After spending several years figuring out how to mount 0.5mm qfps and 1mm BGAs to PCBs, I find myself longing for the old days of wire-wrapping.

I can attach FPGAs to PCBs, but the process of designing a working PCB with an FPGA, RAM, possibly a configuration flash, etc. has turned out to be a miserable disappointment. Bad CAD software, absurdly slow turn-around time, and my own issues with reading documentation make the process last months at a time. This pace virtually guarantees that I forget what I was trying to do by the time a new revision of the board rolls in. I have to find a faster way to work.

If I had a better way to prototype and test a design before rolling a PCB, it would go much faster.

Designing a PCB is great if you are going to make at least a dozen objects. Most of what I do, I am lucky to wind up with one. PCB design is not a great investment of time for me.

I tried making breakout boards. With a stock of bare FPGA boards, memory boards, platform flash, etc in a breadboard-friendly form, I can just plug away at a prototype and not waste a month because I missed a wire or misunderstood what a reference manual said. But breadboards are awful creatures, with very flaky connections and noise characteristics that make them almost useless.

So I am looking at wire-wrapping again. I have to admit that I love the process. I soldered up another XC3S50 board with pins facing up just for kicks (another perfect QFP soldering job 8) on the hotplate), and whipped out my WSU-30M. One wire to LED for testing. What a joy!

Related topics:
Techniques for reliable high-speed digital circuits
Wire-wrapping page at Wilson Mines Co.

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Author:  enso [ Thu Jun 13, 2013 4:26 am ]
Post subject:  Re: Wire-wrapping Xilinx FPGAs
Here is an XCF01 platform flash to match:
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Author:  BigEd [ Thu Jun 13, 2013 4:31 am ]
Post subject:  Re: Wire-wrapping Xilinx FPGAs
Hi enso
are these commercial boards? Do you have links to a product page?
Cheers
Ed
Author:  enso [ Thu Jun 13, 2013 4:34 am ]
Post subject:  Re: Wire-wrapping Xilinx FPGAs
BigEd wrote:
are these commercial boards? Do you have links to a product page?

Nah, I made them.

I used cheap breakaway pin headers that come in rows of 40 pins. I have to figure out a better way to remove the plastic sleeve without bending the pins. They work well with the tool, and look good for 2, possibly 3 layers of wrapping.
Author:  BigEd [ Thu Jun 13, 2013 4:52 am ]
Post subject:  Re: Wire-wrapping Xilinx FPGAs
I see!
Author:  Arlet [ Thu Jun 13, 2013 5:35 am ]
Post subject:  Re: Wire-wrapping Xilinx FPGAs
Any idea what kind of speed you can achieve from one board to another ?
Author:  enso [ Thu Jun 13, 2013 6:35 am ]
Post subject:  Re: Wire-wrapping Xilinx FPGAs
Arlet wrote:
Any idea what kind of speed you can achieve from one board to another ?

Not yet!
I would think if you are careful you can keep the connections pretty short. This board was originally for breadboarding - for wire-wrapping I will make boards with grids of pins.
Author:  Arlet [ Thu Jun 13, 2013 6:47 am ]
Post subject:  Re: Wire-wrapping Xilinx FPGAs
If you can spare the room, putting in some termination resistors could be useful.
Author:  GARTHWILSON [ Thu Jun 13, 2013 7:52 am ]
Post subject:  Re: Wire-wrapping Xilinx FPGAs
Time for the sticky topic "Techniques for reliable high-speed digital circuits." It includes wire-wrapping and prototyping, and has lots of links too.
Author:  enso [ Thu Jun 13, 2013 2:59 pm ]
Post subject:  Re: Wire-wrapping Xilinx FPGAs
GARTHWILSON wrote:
Time for the sticky topic "Techniques for reliable high-speed digital circuits."

Indeed. There are a few other topics covering similar material (if anyone remembers where let me know). I will edit the top post to point to them to avoid repeating of old discussions. I am sorry if some of you think I am just repeating an old topic.

I would like to stick to the specifics of Xilinx chips here, in the context of prototyping pre-PCB designs and mixed PCB/wire-wrap prototyping techniques.

My primary goal (for now) is to wire up the components of a minimal XC3S50 with a flash, crystal and a SRAM. Once that works I will feel confident enough that I can make a PCB with these components (possibly without the RAM). That board can in turn be wire-wrapped to a larger prototype.

One point I am struggling with is that for prototyping with the goal of making a PCB you want to keep your options open. That is why devboards are less useful for me. For instance if I wire a SRAM to a bunch of pins on a board for further prototyping, what if I decide that I want to move the SRAM to a different set of pins? That happens to me all the time designing PCBs and finding opportunities for connecting chips, especially on 2-layer boards. That is why I am hesitant about the putting the SRAM on the final prototype board. Things like the program flash have no other place to go, so that is not an issue. A crystal should probably plug in to allow different values.

I am would like to explore this technique with larger and newer FPGAs, such as the Spartan6. My capabilities are somewhat limited with the number of IOs I can bring out - perhaps 4 rows from each side with 2-layer boards. That's more than enough as far as I am concerned (since the limit remains in the final PCB as well). There are always larger and wider chips if the IOs become a problem. My thinking is to not worry about the 'lost' pins and focus on the design.

It seems obvious to me now that others may benefit - it seems like a sensible way to work. And point out to me if I am doing something really foolish.

Has anyone had experience with termination resistors in similar situation? Wire-wrapping fast circuits or hybrid PCB/wire-wrapped environments?
Author:  ElEctric_EyE [ Fri Jun 14, 2013 2:27 am ]
Post subject:  Re: Wire-wrapping Xilinx FPGAs
enso wrote:
Life is funny. After spending several years figuring out how to mount 0.5mm qfps and 1mm BGAs to PCBs, I find myself longing for the old days of wire-wrapping....

See, most people will read this and not give its proper due attention:..."Several years of how to figure out how to mount QFPs and BGAs..." That is quite alot of time to perfect a method. The knowledge you pass on for us people knowledgeable enough to read and listen, can cut that time in half at least. I would invest 4+ months with PCB board design in a high speed (100+MHz) project (I have 2x now). But if you don't need such high speed (CRAY supercomputers were known for 80MHz operation), go with the wire wrap. Surely it will be much faster development than 3-4 months of a PCB board design...

What sort of confuses me is that with so many available pins on the FPGA, you could assign every pin on the RAM.

You almost mastered BGA mounting, why do you limit yourself to a XC3S50? Are you after 5V compatibility? What version of ISE are you using?
Author:  enso [ Fri Jun 14, 2013 3:21 am ]
Post subject:  Re: Wire-wrapping Xilinx FPGAs
ElEctric_EyE wrote:
Several years
Not as a full-time pursuit, although some of the time, pretty close. Over five mounting qfps and such. Actually etched my first board from a laser output out of a Mac Plus/LaserWriter in '87.

Wire wrap can be used for prototyping high speed circuits. At the very least, you can verify that your connections are right. I imagine (we'll see how it works out) working on a PC board CAD with a wrapped prototype nearby. When you realize that some connections need to be moved, you can test it with your wrapped prototype, perhaps with a slower clock. When done, you can be certain that there are no stupid wiring errors in your PCB.

Quote:
What sort of confuses me is that with so many available pins on the FPGA, you could assign every pin on the RAM.

Exactly, so what may work in one prototype may not make sense in another. That's why I am loathe to build a prototyping board containing a pre-wired SRAM. You may want a 16-bit SRAM for your 65org16.

Quote:
You almost mastered BGA mounting, why do you limit yourself to a XC3S50? Are you after 5V compatibility?

I don't think XC3S50 is really 5V compatible - although I think you can fudge it.
Also there are at least two 6502 cores (Arlet's and MichaelM's) that fit, not to mention many picoblazes. I feel that there is a lot of work to be done bottomfishing.

Quote:
What version of ISE are you using?

13.3 (last one to officially support XDL, although I hear later ones still do).
Author:  enso [ Fri Jun 14, 2013 4:37 am ]
Post subject:  Re: Wire-wrapping Xilinx FPGAs
Wired up the Platform Flash. Success - recognized by Impact. Stores configuration. Getting the hang of it.

Newly-ordered wire has fatter insulation than my old stock, giving me some trouble.
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