This is a summary of the various flavours of 65Org16 core and their implementation status.

(The 65Org16 is a 16-bit extension of the 6502 - the simplest possible such extension - with 16-bit bytes and a 32-bit address space. As a spec, it could be implemented as a new design or as a variant of an existing 6502 core. So far all the implementations are based on Arlet's 6502 core.)

For details of the following, see the index of active threads. If there are errors, let me know and I'll edit.

- 65Org16
The original and intentionally minimal implementation. Seen working on FPGA but only using internal memory. Or, possibly using an external x16 memory on one of EEye's dev boards? Two assemblers available, two emulators, and a minimal monitor program.

- 65Org16-shiftmultiply
An incomplete and abandoned attempt at adding a B register, a multiply instruction, and multi-bit shifts.

- 65Org16.b
Stable but not necessarily final variant with 16 accumulators, 3 index registers. Extra shift/rotate on first 4 accumulators. Stack and zeropage relocatable using base pointers. Some accumulator-to-accumulator arithmetic and logic. Assembly support using a macro file. Probably seen working on FPGA (need clarification)

- 65org16.c
An inconclusive discussion, exploring an idea for 16 registers all with equal capabilities (possibly with the exception of a shift distance register)

- 65Org16.d
Ideas for extending the b core, with more choices for multiplication operands and with exchange operations between pairs of registers.

Note also that the 65Org32 has been described but not implemented: it's a machine with 32-bit bytes, and therefore single-byte addresses. To implement it all the two-byte accesses that 6502 cores do for indirects and push/pull of addresses need to be reduced to single-byte accesses.

A further unnamed idea (perhaps the 65Org1616) is a 65Org32 reduced to 16-bit bytes. Address space is only 64k but addresses are single-byte.

(Edit to add:) Yet another unamed idea (I like 65Org24) is a 65Org32 with merged operands, so that every instruction is self-contained in a single word.

Again, please supply details, clarifications or corrections. We have many threads some of them very long and I will have missed something.

Cheers
Ed