Since I'm forced to learn proper Verilog syntax, and sometimes I feel like a monkey typing almost randomly to achieve some Shakespeare novel, I prefer typing as little as possible and so I think I am learning some shortcuts. But I've come across a shortcut that appears to work only sometimes. Other times ISE13.4 sees it as a straight "syntax error".
I will post Arlet's main.v module which I've modified with his permission. I've modified it even further today and the latest modifications meld the X & Y pixel counters into the output register for the external SyncRAM address. It works, but I'm posting not for questions about functionality (although that would be useful too!), but observe some of the syntax that ISE actually passes. But only sometimes. Early on, it let's me do
/*
* top level module
*
* (C)2012 Arlet Ottens <arlet@c-scape.nl>
* -modified by ElEctric_EyE-
*/
module main(
input clk100,
input [15:0] SRD, //SyncRAM data
output pclk_out,
output SRCLK, //SyncRAM clock
output [4:0] red,
output [5:0] green,
output [4:0] blue,
output vsync,
output hsync,
output reg DACBLANKn = 1,
output reg SRCS = 1, //SyncRAM CS, active high
output reg WEn = 1, //SyncRAM WE, active low
output reg [20:0] SRA //SyncRAM Address
);
wire [15:0] rgb;
assign blue = rgb[4:0],
green = rgb[10:5],
red = rgb[15:11];
wire fifo_write,
fifo_full;
reg [15:0] fifo_data;
wire pclk0,
vtrigger;
/* pixel clock output using DDR flipflop */
ODDR2 ODDRA (
.Q(pclk_out),
.C0(pclk),
.C1(~pclk),
.CE(1'b1),
.D0(1'b1),
.D1(1'b0),
.R(1'b0),
.S(1'b0)
);
/* SyncRAM Clock output also using DDR flipflop */
ODDR2 ODDRB (
.Q(SRCLK),
.C0(dcm_clk100),
.C1(~dcm_clk100),
.CE(1'b1),
.D0(1'b1),
.D1(1'b0),
.R(1'b0),
.S(1'b0)
);
/* clock buffers */
IBUFG IBUFG_clk( .I(clk100), .O(dcm_clk100) );
BUFG BUFG_clk( .I(dcm_clk100), .O(clk) );
BUFG BUFG_PCLK( .I(pclk0), .O(pclk) );
/* Use DCM to generate 25 MHz VGA pixel clock from 100 MHz main clock */
DCM_SP #(
.CLKDV_DIVIDE(4.0),
.CLKFX_DIVIDE(8),
.CLKFX_MULTIPLY(2),
.CLKIN_DIVIDE_BY_2("FALSE"),
.CLKIN_PERIOD(10.0),
.CLKOUT_PHASE_SHIFT("FIXED"),
.CLK_FEEDBACK("1X"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
.DLL_FREQUENCY_MODE("LOW"),
.DUTY_CYCLE_CORRECTION("TRUE"),
.PHASE_SHIFT(0),
.STARTUP_WAIT("FALSE")
) DCM_SP_inst (
.CLKFX(pclk0), // 0 degree DCM CLK output
.CLKFB(pclk), // DCM clock feedback
.PSEN(1'b0), // no variable phase shift
.CLKIN(dcm_clk100), // Clock input (from IBUFG, BUFG or DCM)
.RST(1'b0)
);
//wire clk;
/*
* VGA generator
*/
vga vga(
.clk(clk),
.pclk(pclk),
.hsync(hsync),
.vsync(vsync),
.fifo_data(fifo_data),
.fifo_write(fifo_write),
.fifo_full(fifo_full),
.rgb(rgb) ,
.vtrigger(vtrigger)
);
/*
* when vtrigger is pulsed, generate new frame by sending 640x480 pixels
* to FIFO.
*/
reg [10:0] x = 0;
reg [9:0] y = 0;
wire xdone = (x == 639) && !fifo_full;
wire ydone = (y == 480);
wire [20:0] SRAtemp;
assign SRAtemp[10:0] = x,
SRAtemp[19:11] = y,
SRAtemp[20] = 0; //possible future bank switch bit
/*
* count x, reset at end of line, and pause when FIFO is full
*/
always @(posedge clk)
if( vtrigger || xdone )
x <= 0;
else if( !fifo_full )
x <= x + 1;
/*
* count y, reset at start of new frame, and increment at end
* of line. Pause when FIFO is full.
*/
always @(posedge clk)
if( vtrigger )
y <= 0;
else if( xdone && !ydone )
y <= y + 1;
/*
* only write fifo during active pixels
*/
assign fifo_write = !ydone;
/*
* SyncRAM address generator
*/
always @(posedge clk)
if( vtrigger )
SRA <= 0;
else if ( !fifo_full )
SRA <= SRAtemp;
/*
* SyncRAM output into FIFO
*/
always @*
fifo_data <= SRD; // RAM data
endmodule
Login
Register
FAQ
Search
