Ruud:
I had looked at your website several months ago, and was certainly impressed by the dedication and the perserverance needed to built your CPU. Tip of the hat to you.
On the subject of your question, I will suggest considering an implementation based on a bit serial, or a nibble serial implementation. This is the next approach that I will take on my FPGA-based 65C02 core, but it is something that you can also use in your implementation. You may have to run the ALU section at a sufficiently higher frequency in order to maintain a reasonable overall performance.
If you implemented the ALU as a nibble mode, the '181 ALU and '174 D-register on the ALU output and '74 D-FF on the nibble carry out should be sufficient to perform the sums and other operations. Furthermore, since the basic ALU operation is nibble wide, it may work to your advantage in the implementation of the BCD mode for the ADC/SBC instructions.
Also, you would have several different ways to multiplex the appropriate sections onto the ALU inputs. For example, octal registers followed by '240/'241 dual 4-bit tri-state drivers, or any number of other combinations of registers, tri-state buffers, and multiplexers. I daresay that you should be able to operate your core at a high enough frequency to achieve a respectable instruction execution rate.
I suspect that 12-16 MHz should be something you could achieve as long as you don't use TTL parts with extremely fast edge rates, i.e. do not use FCT, BCT, or similar logic families. You may have to use series damping resistors in the ALU section, but I doubt that they would be necessary for the rest of the CPU.
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