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K1 Controller Board with Video Capture

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ElEctric_EyE

Post subject: K1 Controller Board with Video Capture

Posted: Wed Dec 18, 2013 3:53 pm

Joined: Mon Mar 02, 2009 7:27 pm
Posts: 3258
Location: NC, USA

I decided to start a new thread on the Controller Board because I was having difficulty finding a decent camera module. In the end I decided to use an HDMI video input. This way a camera could be hooked up or any other HDMI video source outputting 1920x1080 @60Hz.

The IC I was looking at is an Analog Devices ADV7441. It is a video digitizer with the capability to handle many types of video inputs, even HDMI. It also handles the audio present in the HDMI stream. A very nice looking chip in a 144-pin QFP package, although I am prepared for a challenge.
EDIT: This IC is presently not recommended for new designs, so I am going to use an ADV7611 HDMI Receiver. It only has a single HDMI input and also can strip out the audio from the multimedia stream with the help of an SSM2604 audio codec. The receiver comes in an easy to handle 96-pin QFP package. There is a 1/8" dual stereo jack for audio out and audio in for experimentation with the audio codec IC. The audio codec is in a 20-pin QFN package.

There are 2 fast 2Mx18 SyncRAM's onboard as well, each with their own dedicated address and data buses. They can be used as video frame buffers, or maybe 1 as a frame buffer and 1 for sprite data.

It also has a 3 x USB to UART interfaces using the FTDI FT230X. Connections to a PC for file transfer, separate keyboard and separate mouse should be possible.

A DS1085L programmable frequency generator is onboard as well. It can be used in conjunction with the FPGAs PLL to generate virtually any frequency needed for the project.

A TSC2003 resistive touchscreen controller is onboard as well for experimentation.

At the center of all this will be a Xilinx XC6SLX25-3FT256, a 256-pin 1mm BGA, with a SPI FLASH PROM. Only 2 Voltages are needed for the FPGA, 3.3v for VCCaux & VCCO and 1.2v for VCCint. The FPGA will control the HDMI receiver, audio codec, touchscreen controller and programmable oscillator through a common I2C bus.

So the plan is to digitize incoming HDMI video into 24 bpp, take the least 5-6-5 bits from the RGB stream, mix it with the onboard videoRAM and then send the stream to 1 Parallel Video Board which will output the 1080p video through an older style VGA connector to an HD monitor. The original idea was to use at least 3 PVB's, but the pins were not there on this 256-pin Spartan 6. A successor to this K1 controller board will be able to control 6 PVB's. As it stands the 1 PVB will receive commands using an 8 bit parallel interface. Also, the controller board can choose which FPGA PROM the PVB should be programmed with.

Big dreams indeed, but I will take it one step at a time. The first step, after the board layout, is properly mounting the BGA and controlling the 1 PVB. Some discussion of how I will attempt this has already taken place.

Here is the constraints file that locks in the pin locations for ISE for program the FPGA. A great way to re-check a design, found just a few problems that I corrected.

Code:

         # Synchronous Ram #1 Signals #
NET "SRAddr[0]" LOC = PA4 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //VREF
NET "SRAddr[1]" LOC = PE7 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //P_GCLK
NET "SRAddr[2]" LOC = PA3 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //VREF
NET "SRAddr[3]" LOC = PB3 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[4]" LOC = PA2 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[5]" LOC = PB2 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[6]" LOC = PF4 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[7]" LOC = PF3 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[8]" LOC = PE4 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[9]" LOC = PD5 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[10]" LOC = PC5 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[11]" LOC = PE6 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[12]" LOC = PD6 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[13]" LOC = PA8 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[14]" LOC = PB8 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[15]" LOC = PA7 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[16]" LOC = PC7 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[17]" LOC = PA6 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[18]" LOC = PB6 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[19]" LOC = PA5 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[20]" LOC = PB5 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[0]" LOC = PD6 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[1]" LOC = PD8 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[2]" LOC = PC8 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //VREF
NET "SRD[3]" LOC = PE8 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //N_GCLK
NET "SRD[4]" LOC = PE10 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //P_GCLK
NET "SRD[5]" LOC = PD11 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[6]" LOC = PE11 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[7]" LOC = PD12 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[8]" LOC = PB1 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[9]" LOC = PC3 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[10]" LOC = PC1 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[11]" LOC = PC2 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[12]" LOC = PD1 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[13]" LOC = PE1 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[14]" LOC = PE3 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[15]" LOC = PF2 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //P_GCLK
NET "SRWEn" LOC = PF5 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRCLK" LOC = PF1 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //N_GCLK

 # Synchronous Ram #2 Signals #
NET "SRAddr[0]" LOC = PT6 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[1]" LOC = PP6 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[2]" LOC = PT7 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //N_GCLK
NET "SRAddr[3]" LOC = PR7 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //P_GCLK
NET "SRAddr[4]" LOC = PT8 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //P_GCLK
NET "SRAddr[5]" LOC = PR9 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[6]" LOC = PK5 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[7]" LOC = PH4 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //P_GCLK
NET "SRAddr[8]" LOC = PL4 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[9]" LOC = PM4 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[10]" LOC = PL5 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[11]" LOC = PK1 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[12]" LOC = PK2 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[13]" LOC = PP4 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[14]" LOC = PT4 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRAddr[15]" LOC = PR5 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //D0-D15
NET "SRAddr[16]" LOC = PT5 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //RDWR_B_VREF
NET "SRAddr[17]" LOC = PM6 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //D0-D15
NET "SRAddr[18]" LOC = PP8 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //P_GCLK
NET "SRAddr[19]" LOC = PP7 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //P_GCLK
NET "SRAddr[20]" LOC = PN8 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //N_GCLK
NET "SRD[0]" LOC = PL1 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[1]" LOC = PL3 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[2]" LOC = PM1 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[3]" LOC = PM2 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[4]" LOC = PN1 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[5]" LOC = PN3 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[6]" LOC = PP1 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[7]" LOC = PP2 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[8]" LOC = PN6 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //D0-D15
NET "SRD[9]" LOC = PN5 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //D0-D15
NET "SRD[10]" LOC = PP5 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //D0-D15
NET "SRD[11]" LOC = PN4 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[12]" LOC = PM5 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[13]" LOC = PM3 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //VREF
NET "SRD[14]" LOC = PR2 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRD[15]" LOC = PR1 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "SRWEn" LOC = PK3 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //P_GCLK
NET "SRCLK" LOC = PH4 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //P_GCLK

 # USB TO UART Signals #
NET "PC_TX" LOC = PJ3 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "PC_RX" LOC = PJ1 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "MOUSE_TX" LOC = PH2 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "MOUSE_RX" LOC = PH1 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "KB_TX" LOC = PG3 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "KB_TX" LOC = PG1 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
 
  # I2C Signals #
NET "SCL" LOC = PJ11 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //P_GCLK
NET "SDA" LOC = PM9 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //P_GCLK

 # HDMI Receiver #
NET "P23" LOC = PA9 |IOSTANDARD = LVCMOS33;  //N_GCLK
NET "P22" LOC = PC9 |IOSTANDARD = LVCMOS33;  //P_GCLK
NET "P21" LOC = PB10 |IOSTANDARD = LVCMOS33;  //P_GCLK
NET "P20" LOC = PA10 |IOSTANDARD = LVCMOS33;  //N_GCLK
NET "P19" LOC = PC11 |IOSTANDARD = LVCMOS33;  //USER I/O
NET "P18" LOC = PA11 |IOSTANDARD = LVCMOS33;  //USER I/O
NET "P17" LOC = PB12 |IOSTANDARD = LVCMOS33;  //USER I/O
NET "P16" LOC = PA12 |IOSTANDARD = LVCMOS33;  //VREF
NET "P15" LOC = PA13 |IOSTANDARD = LVCMOS33;  //USER I/O
NET "P14" LOC = PE12 |IOSTANDARD = LVCMOS33;  //VREF
NET "P13" LOC = PA14 |IOSTANDARD = LVCMOS33;  //USER I/O
NET "P12" LOC = PB14 |IOSTANDARD = LVCMOS33;  //USER I/O
NET "P11" LOC = PB16 |IOSTANDARD = LVCMOS33;  //A0-A25
NET "P10" LOC = PC16 |IOSTANDARD = LVCMOS33;  //A0-A25
NET "P9" LOC = PC15 |IOSTANDARD = LVCMOS33;  //A0-A25
NET "P8" LOC = PD16 |IOSTANDARD = LVCMOS33;  //A0-A25
NET "P7" LOC = PD14 |IOSTANDARD = LVCMOS33;  //A0-A25
NET "P6" LOC = PE16 |IOSTANDARD = LVCMOS33;  //A0-A25
NET "P5" LOC = PF12 |IOSTANDARD = LVCMOS33;  //A0-A25
NET "P4" LOC = PE15 |IOSTANDARD = LVCMOS33;  //A0-A25
NET "P3" LOC = PF14 |IOSTANDARD = LVCMOS33;  //A0-A25
NET "P2" LOC = PF16 |IOSTANDARD = LVCMOS33;  //A0-A25
NET "P1" LOC = PF13 |IOSTANDARD = LVCMOS33;  //A0-A25
NET "P0" LOC = PF15 |IOSTANDARD = LVCMOS332;  //A0-A25
NET "LLC" LOC = PJ6 |IOSTANDARD = LVCMOS33;  //P_GCLK
NET "DE" LOC = PG16 |IOSTANDARD = LVCMOS33;  //A0-A25
NET "HSYNCin" LOC = PG12 |IOSTANDARD = LVCMOS33;  //A0-A25
NET "VSYNCin" LOC = PH15 |IOSTANDARD = LVCMOS33;  //P_GCLK

 # Bi-Directional Communication Interface #
NET "D0" LOC = PL13 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //VREF
NET "D1" LOC = PJ12 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //N_GCLK
NET "D2" LOC = PT9 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "D3" LOC = PL10 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "D4" LOC = PM11 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "D5" LOC = PP12 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //D0-D15
NET "D6" LOC = PN12 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //D0-D15
NET "D7" LOC = PJ13 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //P_GCLK
NET "CLK" LOC = PR12 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "R_W" LOC = PT14 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "PVB1RDY" LOC = PT12 |IOSTANDARD = LVCMOS33;  //USER I/O
NET "PVB1BE" LOC = PT13 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "PVB1PROM1_2" LOC = PH15 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //A0-A25
NET "PVB1PROGRAM" LOC = PT15 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O

 # RGB Video Signals to PVB1#
NET "HSYNCout" LOC = PR14 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "VSYNCout" LOC = PP16 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "B4out" LOC = PR15 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "B3out" LOC = PR16 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "B2out" LOC = PP15 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //FCS/FWE
NET "B1out" LOC = PN16 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //A0-A25
NET "B0out" LOC = PN14 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //A0-A25
NET "G5out" LOC = PM12 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "G4out" LOC = PM16 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //FCS/FWE
NET "G3out" LOC = PM15 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //FCS/FWE
NET "G2out" LOC = PL14 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //FCS/FWE
NET "G1out" LOC = PL16 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //FCS/FWE
NET "G0out" LOC = PL12 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //USER I/O
NET "R4out" LOC = PK16 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //A0-A25
NET "R3out" LOC = PJ14 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //P_GCLK
NET "R2out" LOC = PJ16 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //N_GCLK
NET "R1out" LOC = PH16 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //A0-A25
NET "R0out" LOC = PG14 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //A0-A25
NET "PCLKout" LOC = PK14 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //N_GCLK

 # Programmable Clock Input from DS1085L #

NET "ProCLKin" LOC = PK11 |IOSTANDARD = LVCMOS33;  //N_GCLK
 
 # Programmable Clock Output from FPGA #

NET "ProCLKout" LOC = PM7 |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 12;  //N_GCLK 

EDIT: (11/10/2014) Redefined the goals, added board layout and .ucf constraints file.
EDIT: (11/12/2014) Added missing CLK signal to bidirectional interface in .ucf file

Attachments:

11-10-2014 12-45-44 PM.jpg [ 1.99 MiB | Viewed 2948 times ]

_________________
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Last edited by ElEctric_EyE on Thu Nov 13, 2014 1:22 am, edited 5 times in total.

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ElEctric_EyE

Post subject: Re: K1 Controller Board with Video Capture

Posted: Fri Dec 20, 2013 3:06 am

Joined: Mon Mar 02, 2009 7:27 pm
Posts: 3258
Location: NC, USA

I also want to include some RF Transmitters/Receivers on-board. The Receiver and Transmitter seem to be great choices with many frequency options.
Looks like those packages are old now, I had looked them up about 2 years ago as I found them in a professionally made circuit board just lying around outside of a new shop I was working at. Maybe accidentally discarded?... They had appeared to be used in an automatic irrigation system, where cork 'springs' were plugged into the ground and would trigger the transmitter to fire the irrigation after so many hours after being dry the cork 'springs' would be naturally compressed. The hysteresis was set by a potentiometer... Yes, I like to tear things apart!

They're in a new package now and still available from LINX Technologies.

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ElEctric_EyE

Post subject: Re: K1 Controller Board with Video Capture

Posted: Sun Dec 22, 2013 5:08 pm

Joined: Mon Mar 02, 2009 7:27 pm
Posts: 3258
Location: NC, USA

I did a preliminary layout of the 256-pin BGA according to Xilinx's UG112, only the vias are not as small as they should be. As I am using ExpressPCB 4-layer service, I'm confined to certain rules, but I don't think it'll be a problem.

An advantage of using a SPI FLASH (16Mbit) as the FPGA PROM as that the FPGA uses only 2 voltages: VCCInt (1.2V) and VCCO/VCCAux(3.3V). With careful routing, and a few pins sacrificed as NC(not connected), I was able to put the 1.2V plane within the rest of the 3.3V power plane. I'm going off of Arlet's 6502 sandbox design where he used a SPI Flash for a smaller Spartan 6.

Confident that the powers and ground pins are 100% correct, it is time to re-check the Dedicated pin locations and add the FLASH to the layout.

Adding bypass capacitors is going to be a real trick, but I have a plan.

EDIT (10/23/14): Added link.

Attachments:

FTG256 BGA.jpg [ 462.13 KiB | Viewed 3401 times ]

Power plane.jpg [ 99.78 KiB | Viewed 3401 times ]

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Last edited by ElEctric_EyE on Thu Oct 23, 2014 8:28 pm, edited 1 time in total.

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ElEctric_EyE

Post subject: Re: K1 Controller Board with Video Capture

Posted: Mon Oct 20, 2014 5:35 pm

Joined: Mon Mar 02, 2009 7:27 pm
Posts: 3258
Location: NC, USA

Yesterday, after comparing some video digitizers/HDMI receiver IC's from Analog Devices, I decided to go with the ADV7611.
It is classified as an HDMI receiver. Turns out I don't need a digitizer like I had thought I did.

What got me very interested in this IC was an already proven design built around it and a videoDAC I am already using from Analog, the ADV7125. The HDMI to VGA converter board is explained in the circuit note.

In the design I am thinking about, I won't need the videoDAC on this K1 controller board, it will just need to pass on the RGB data and clock to the FPGA. However, I would like to include the I2C switch for EDID experimentation and the SSM2604 audio codec to strip audio from the incoming HDMI.

I've looked over their schematics and BOM and have started my own parts list. When it is complete, I'll update the head post on this thread...

Some other additions I'm adding are:
3x USB to UARTs based on FTDI's FT230X. 1 for keyboard input, 1 for mouse input, and 1 for file/data transfer from a PC.
A TSC2003 touchscreen controller for a resistive touchscreen input.
3 wireless transceiver modules.
A large SPI Serial Flash IC for data storage.
A 256-pin XC6SLX25 with a dedicated 16Mbit SPI Flash for FPGA PROM.
2 2Mx18 4ns SyncRAMs.
A 96-pin connector to control other Parallel Video Boards and to pass the HDMI video stream to the 1st PVB.
A mini SD Card slot for quick removable storage.

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Last edited by ElEctric_EyE on Thu Oct 23, 2014 8:30 pm, edited 2 times in total.

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ElEctric_EyE

Post subject: Re: K1 Controller Board with Video Capture

Posted: Mon Oct 20, 2014 7:35 pm

Joined: Mon Mar 02, 2009 7:27 pm
Posts: 3258
Location: NC, USA

For the RF transceiver modules (not bluetooth), I'm leaning towards the HUM-900-DT by LINX technologies. They're $20US/ea presently at Digi-Key.

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ElEctric_EyE

Post subject: Re: K1 Controller Board with Video Capture

Posted: Sun Oct 26, 2014 5:51 pm

Joined: Mon Mar 02, 2009 7:27 pm
Posts: 3258
Location: NC, USA

Today I tried to finish making custom IC & I/O Connector layouts in ExpressPCB. If all the IC's/Connectors fit within 21sqin, I'll commit my time to this design for production. Hopefully won't be 4 months like the last few boards.
It's preliminary...
The input power connector and VReg's (which will be placed on the bottom) are the only things missing at this point...

Initial fitment:

Attachments:

K1.Initial.jpg [ 450.92 KiB | Viewed 3173 times ]

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ElEctric_EyE

Post subject: Re: K1 Controller Board with Video Capture

Posted: Mon Oct 27, 2014 4:11 pm

Joined: Mon Mar 02, 2009 7:27 pm
Posts: 3258
Location: NC, USA

It's mentally difficult to make the transition, from Verilog and a limited amount of software programming, to PCB design.

I decided to share the progress I make daily. Hopefully it will be useful to some home brew folks out there willing to tackle BGA packages for their design.

Added micro-SD Card connector on the top side, middle right, and started the wiring on the left side of the board.
Presently, I have 3 pages from data sheets laid out in front of me showing the pinouts of 3 ICs at this point: The USB to UART IC's, the 2Mx18 SyncRAMs, and the Spartan 6.

Interfacing the SyncRAMs is the next challenge I'm working up to. What I do currently is to count the number of signal pins on each side of the SyncRAMs and then count the number of available pins on the FPGA that are closest to them, above (RED) and below (GREEN) the board

Attachments:

2014-10-27_12-04-06.jpg [ 467.27 KiB | Viewed 3144 times ]

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ElEctric_EyE

Post subject: Re: K1 Controller Board with Video Capture

Posted: Wed Oct 29, 2014 12:18 am

Joined: Mon Mar 02, 2009 7:27 pm
Posts: 3258
Location: NC, USA

About 2 more hours spent on connecting SyncRAM #2. Was able to move it closer to the FPGA. I went through about 3 iterations where I moved the RAM closer and closer to the FPGA.
This is one reason I'm not so keen on exact positions of the trace corners. Another reason is that I don't think they will even be visible on the produced board. I used to type the exact coordinates in by hand until there were no 'steps'visible in the diagonal, vertical, and horizontal traces at higher magnifications. It's not worth the time and effort to make it perfect, especially not this board which is pretty much a prototype...

What I do pay close attention to is minimizing trace length between the high speed SyncRAMs and FPGA.

Maybe another 2 hours tomorrow and SyncRAM #1 will be wired up. That would be a step up in my learning curve for this board!

Tonight I'll finish up the primary wiring from the FFC connector of the TSC2003 touchscreen controller in the bottom left. This is abit of a hack since I'm using a leftover touchscreen puchase from Ebay originally meant for a Kocaso m1050s Android tablet. There was no data sheet included, so no way to know if I'm correctly matching up X+, X-, Y+, Y-. I'll make it possible for the 4 connections to be jumpered at this point.

Attachments:

2014-10-28_20-06-55.jpg [ 524.58 KiB | Viewed 3111 times ]

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ElEctric_EyE

Post subject: Re: K1 Controller Board with Video Capture

Posted: Wed Oct 29, 2014 1:36 am

Joined: Mon Mar 02, 2009 7:27 pm
Posts: 3258
Location: NC, USA

Prepping SyncRAM1 IC by removing all No Connections like was done on SyncRAM2.

Also IC's and connectors are now labelled.

There were enough changes at this point so I made a new backup.

BOM soon.

Attachments:

2014-10-28_21-29-38.jpg [ 524.71 KiB | Viewed 3104 times ]

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ElEctric_EyE

Post subject: Re: K1 Controller Board with Video Capture

Posted: Thu Oct 30, 2014 12:48 am

Joined: Mon Mar 02, 2009 7:27 pm
Posts: 3258
Location: NC, USA

Found a couple of Power Supply wiring errors right there at the bottom right SyncRAM2 whilst wiring up SyncRAM1.

Added provisions for pullups on SCL/SDA lines on the Touchscreen countroller.

Added MCP1826 1.8VReg for FPGA VCCInt Core.

Wired in SyncRAM1. Both SyncRAMs are always active. The nice thing is with an FPGA this wide is that each SyncRAM has it's own data bus and address bus.

I would like to wire in the ADV7611 HDMI Receiver next, but I need to start a .ucf file creating pin assignments for the FPGA as another check for this schematic-less design.
Also I need to check I2C addresses for any conflicts for all the IC's present.

Attachments:

2014-10-29_20-30-18.jpg [ 581.75 KiB | Viewed 3074 times ]

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Aslak3

Post subject: Re: K1 Controller Board with Video Capture

Posted: Thu Oct 30, 2014 12:17 pm

Joined: Mon Aug 05, 2013 10:43 pm
Posts: 258
Location: Southampton, UK

I am utterly inexperience when it comes to these kinds of devices, but I had always assumed that those kind of BGA packaged ICs needed a lot more then 4 layers on the board? What are the trace and via dimensions on the board?

Also, would a simpler FPGA do this job? BGA looks like it adds a whole new level of difficulty. Or is the choice "for the challenge"

It's a very interesting project. Are you going to encode the video in a particular format, or will it just write out raw frames? I trust you will keep us updated with your progress!

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ElEctric_EyE

Post subject: Re: K1 Controller Board with Video Capture

Posted: Thu Oct 30, 2014 8:40 pm

Joined: Mon Mar 02, 2009 7:27 pm
Posts: 3258
Location: NC, USA

Aslak3 wrote:

You're correct. In order to utilize all of the 'pins' more than 4 layers is needed. I am unable to route out about 22 'pins' so they are wasted...I wish I could find it, but Xilinx has a User's Guide for PCB Planning and goes in-depth on layers needed depending on package size (# of 'pins') and 'pin' spacing. The device I use has 1mm spacing.
I am using .006" trace width. Several different vias are used depending on if they are for power or signal. For signal, I use .026" with .008" hole. Power vias are larger.

Aslak3 wrote:

...Also, would a simpler FPGA do this job? BGA looks like it adds a whole new level of difficulty. Or is the choice "for the challenge"

Yes BGA is most definately a whole new level requiring more skills. I undertook this part of the project out of a need for more 'pins'. The 144-pin QFP package was very limiting for me when I was even designing the first Parallel Video Board with only 1 videoRAM and 16-bit videoDAC.

Aslak3 wrote:

...It's a very interesting project. Are you going to encode the video in a particular format, or will it just write out raw frames? I trust you will keep us updated with your progress!

Thanks alot, I enjoy the feedback!
For now, I envision just getting raw RGB pixel data sent from an HDMI device into the ADV7611 and output all 24-bits into the FPGA.
The first stage is for the FPGA to truncate some bits and transmit 5-6-5 16-bit RGB data to Parallel Video Board for output to an HD monitor that displays 1920x1080.

And now that I wrote this, I realize I won't be able to experiment with EDID, as the final ouput to the VGA connector is on a different board. Maybe the next version of the Parallel Video Board will include the scl/sda pins on the VGA connector necessary to communicate with the video monitor.

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ElEctric_EyE

Post subject: Re: K1 Controller Board with Video Capture

Posted: Fri Oct 31, 2014 11:14 pm

Joined: Mon Mar 02, 2009 7:27 pm
Posts: 3258
Location: NC, USA

Shout out to Michael M. He spotted a careless mistake I had made and PM'd me. VCCInt for the Spartan6 FPGA is 1.2V not 1.8V. Thanks!

I'm wiring up the HDMI connector, ESD protection and connections to the ADV7611 according to the CN-0282 (Circuit Note) from Analog Devices. I don't see a license file, so I probably shouldn't take snapshots of their stuff and post. One has to register to see their project.

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BigEd

Post subject: Re: K1 Controller Board with Video Capture

Posted: Sat Nov 01, 2014 3:23 am

Joined: Thu Dec 11, 2008 1:28 pm
Posts: 10986
Location: England

(Sharing small extracts of a copyrighted work for educational and non-profit purposes is OK - it's called fair use. But don't share the whole work without reflection.)

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ElEctric_EyE

Post subject: Re: K1 Controller Board with Video Capture

Posted: Sat Nov 01, 2014 10:51 pm

Joined: Mon Mar 02, 2009 7:27 pm
Posts: 3258
Location: NC, USA

Ok Ed. Thanks for clearing that up!

From Wikipedia, this is the pinout of a mini-HDMI connector.
The pic below it, is a snapshot from page 1 of Analog Devices CN-0282 schematics. Since I have no experience in HDMI, I must tread lightly and copy certain parts from this proven project. The input is the most critical at this point...
U1, U2 & U3 are ESD protection diode arrays. Their part #'s are included in Analog's BOM and are still available through Digikey here in the US. I've added them to my BOM which will be posted soon.

The last 2 days I've had alot of interruptions to deal with, so not much progress. Next 2 days shall be dedicated. :twisted:

Attachments:

mini-HDMI pinout.jpg [ 100.26 KiB | Viewed 2989 times ]

mini HDMI connector.jpg [ 40.83 KiB | Viewed 2989 times ]

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