For my 65k project I have written an analyzer to find the logic equations that should be used to detect, say, a specific opcode or a specific addressing mode.

The output of that looks like:



for absolute addressing for example, or



for the ROL operation. (Note I have 10 bits opcode "address", as I use A8/9 to select my extra opcode pages in the 65k).

Looking at these analysis, one can still only wonder how well these opcodes and addressing modes are distributed in the opcode page, to reduce the number of terms.

Even though I tried to optimized it, I still found I added considerable number of terms to some of the items (e.g. STA went from 7 opcodes and 3 terms to 8 opcodes and 4 terms in the CMOS and 17 opcodes and 9 terms in the 65k. 9 seems to be the maximum number of terms for operations).

So I was thinking how to proceed. Does it make sense to try to optimize the opcode mapping more? On the other hand, in the FPGA this will most likely be a large LUT - and "large" means 1k addresses with 10 inputs (although there will most likely many more than 8 outputs).

And then, how would I program this (in VHDL, but I'd think verilog isn't that much different in this respect). Would I simply do something like (pseudo code, can't remember the VHDL syntax right now):



And then let Xilinx do the optimization?

Thanks for any advice

André

P.S.: I will put my analysis results on the web page together with the analyzer program, but haven't done that yet...