The idea of using register banks could still be useful for the 65OrgXX. Especially with the register file method, it's trivial to make a bigger register file, with some extra index bits connected to a state machine.

Another useful idea from other architectures is an interrupt vector controller. This would consist of a hardware interrupt priority encoder, combined with a table of interrupt vectors. Whenever there's a particular interrupt, the IRQ vector will be replaced with the value from the look up table, so the core would automatically jump to the correct handler. Extra bits from the table could be used to select the register file, for instance.

These things are quite simple to implement. They only take a little bit of logic, and aren't in the critical path.