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Using Xilinx Macros on CPLD
http://forum.6502.org/viewtopic.php?f=10&t=1998		 Page 1 of 1
Author:  streammylife [ Mon Nov 21, 2011 6:52 pm ]
Post subject:  Using Xilinx Macros on CPLD
The CPLD libraries guides lists numerous Macros that are supported in the CoolRunner-II architecture, but I can't figure out how to use them. I'm sure this is incredibly simple but apparently the

library.unimacros;
use unimacros.vcomponents.all;

does not work on CPLD's. Specifcally I would like to use the CB16CE counter Macro described in the libraries guide. Please enlighten me! Thanks!
Author:  ElEctric_EyE [ Mon Nov 21, 2011 10:05 pm ]
Post subject: 
Looks like you are using VHDL?

I would recommend searching Xilinx.com for the HDL library, and how to instantiate it, for the Coolrunner II family. Coolrunner series can easily do 16-bit counters.

Oops, I see you have looked at the library already...
Author:  ElEctric_EyE [ Tue Nov 22, 2011 12:26 am ]
Post subject: 
After rereading your original post I realized the intent of your post.
kc5tja mentioned having problems as well when attempting to use macros in Xilinx ISE briefly here. I know nothing about macro's and barely know HDL, and honestly don't have time to explore this issue yet, but I'd thought I would try to help while I was in here updating an old thread...
Author:  streammylife [ Tue Nov 22, 2011 1:28 am ]
Post subject: 
Unfortunately the UNIMACRO library used to for the macros on Xilinx FPGA's doesn't work with Xilinx CPLD's from what I've read. The CPLD libraries guide says that all the Macro's are compatible with the device I'm using but I can't figure out how to include the Macro library for compilation. I'm a little shocked that I couldn't find this in a 30 second google search but for some reason I still can't figure it out.

I actually just wrote the behavioral logic in VHDL and bypassed the need to use the Macro but I would still like to know for the future.
Author:  ElEctric_EyE [ Tue Nov 22, 2011 12:55 pm ]
Post subject: 
I don't think Xilinx ISE HDL editor will allow you to do what you want. I think you will need a product from Synopsys or Mentor Graphics. These guys have patents on their stuff so Xilinx can't include them in their ISE software.

I may have a solution for you though, it involves using schematic entry and viewing the HDL equivalent, although I think it will only show you Verilog, not VHDL. You create a top-level schematic, choose your CB16CE counter and place it. Then in the Process window, under Design Utilities, View HDL Functional Model.

This is what I see from ISE13.2:
Code:
module CB16CE_HXILINX_top_level(CEO, Q, TC, C, CE, CLR);
   
   parameter TERMINAL_COUNT = 16'b1111_1111_1111_1111;
   
   output             CEO;
   output [15:0]      Q;
   output             TC;

   input          C;   
   input          CE;   
   input          CLR;   
   
   reg    [15:0]      Q;
   
   always @(posedge C or posedge CLR)
     begin
   if (CLR)
     Q <= 16'b0000_0000_0000_0000;
   else if (CE)
     Q <= Q + 1;
     end
   
   assign CEO = TC & CE;
   assign TC = CLR ? 1'b0 : (Q == TERMINAL_COUNT);
   
endmodule


BTW, I could only find the Coolrunner II Libraries Guide for Schematic Entry. Where do you see the one for HDL Entry?
Author:  ElEctric_EyE [ Tue Nov 22, 2011 1:06 pm ]
Post subject: 
I changed my preference to VHDL, here is what I see now for a XC2C32 under ISE13.2, without pin assignments:
Code:
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity FTCE_MXILINX_top_level is
   generic( INIT : bit :=  '0');
   port ( C   : in    std_logic;
          CE  : in    std_logic;
          CLR : in    std_logic;
          T   : in    std_logic;
          Q   : out   std_logic);
end FTCE_MXILINX_top_level;

architecture BEHAVIORAL of FTCE_MXILINX_top_level is
   attribute BOX_TYPE       : string ;
   signal TQ      : std_logic;
   signal Q_DUMMY : std_logic;
   component XOR2
      port ( I0 : in    std_logic;
             I1 : in    std_logic;
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of XOR2 : component is "BLACK_BOX";
   
   component FDCE
      generic( INIT : bit :=  '0');
      port ( C   : in    std_logic;
             CE  : in    std_logic;
             CLR : in    std_logic;
             D   : in    std_logic;
             Q   : out   std_logic);
   end component;
   attribute BOX_TYPE of FDCE : component is "BLACK_BOX";
   
begin
   Q <= Q_DUMMY;
   I_36_32 : XOR2
      port map (I0=>T,
                I1=>Q_DUMMY,
                O=>TQ);
   
   I_36_35 : FDCE
   generic map( INIT => INIT)
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>TQ,
                Q=>Q_DUMMY);
   
end BEHAVIORAL;
Author:  streammylife [ Tue Nov 22, 2011 1:08 pm ]
Post subject: 
The CPLD libraries guide that I'm referring to is:

http://www.xilinx.com/support/documenta ... ll_scm.pdf

For the primitives I select the library at the top of the file:

library UNISIM;
use UNISIM.VComponents.all;

Then I can just map signals to the ports like this:

FDDCPE_FF1 : FDDCPE
port map(
Q => output_signal,
C => clock,
CE => '1',
CLR => clr,
D => input_signal,
PRE => '0'
);

It would be really useful to use the MACRO's in the exact same way.

*Also not sure if it makes any difference but I'm using Xilinx 11.1
Author:  BigEd [ Tue Nov 22, 2011 9:19 pm ]
Post subject: 
welcome!

that manual notes that the macros are only intended for schematic use. I think the general idea for HDL entry is that you let the synthesis infer high level things like shifters and counters. You may need to code up in a specific style for the inference to work, and you may wrap each in counter in a level of hierarchy, but basically you write your own. I can't readily find an example, but this divider example might work and might be helpful:
Code:
module warning_example(Clk_In,Clk_Out);

input Clk_In;
output reg Clk_Out = 0;

reg [28:0] counter = 0;

always @(posedge Clk_In) begin
    counter <= counter + 1'b1;
    if(counter == (100_000_000 - 1)) begin
        counter <= 0;
        Clk_Out <= ~ Clk_Out;
    end
end

endmodule


It's from this forum post - you might find the xilinx forums useful, if you can cook up a good title and describe your problem clearly.

The xst user guide UG627 chapter 5 contains this statement about inference of macros:
Quote:
The general macro generation flow is:
1. Hardware Description Language (HDL) infers macros and submits them to the low-level synthesizer.
2. Low-level synthesizer accepts or rejects the macros depending on the resources required for the macro
implementations.


The trick is to write in an idiom which gets the synthesis tool to recognise what you're doing, and you check that by reading the synthesis report, looking for adders, counters, memories as appropriate.

Hope this helps.
Cheers
Ed
Author:  streammylife [ Tue Nov 29, 2011 9:03 pm ]
Post subject: 
I was able to describe the logic and synthesize what I was looking for, it just seems like it might be helpful to have the ability to explicitly specify the components I would like to use. For instance if I wanted to use a slower component with less gates to save space or vice versa with a faster component. It just irks me that I can utilize the primitives in this manner and can apparently utilize macros on FPGAs, but I can't on the CPLD. Oh well, can't win them all.
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