Elsewhere we touched on the difficulty of fitting a 6502 core into CPLD.

It turns out that Steve Chamberlin, of Big Mess O' Wires fame, has tackled this problem and defined a subset of 6502 which he fits into a CPLD, with a second CPLD to make up a system (with 10-bit address bus)

Tiny CPU

Very interesting stuff there, I've bookmarked his site. Very small opcode list, and very few addressing modes. Still it can do sbc, adc, cmp, 64byte stack, PHA, PHX... I'd be interested to see a speed comparison on Xilinx.

EDIT: I've tried, but there appears to be a missing piece of code for add_sub