Awesome -- that's the confirmation of suspicion I was looking for.
Thanks.
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| WTH does this mean? http://forum.6502.org/viewtopic.php?f=10&t=1981 |
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| Author: | kc5tja [ Mon Oct 31, 2011 3:45 am ] |
| Post subject: | WTH does this mean? |
Xilinx website has no information on this error at all. I'm not sure what this means. Background -- I'm finishing up the top-level module for the PS/2 adapter, and wanted to see if it synthesized. I *do not* have a UCF file for synthesis yet, because I'm not particularly concerned with mapping pins to I/O just yet. I just want to see if my work to date is capable of synthesis. I already know it simulates as expected, though to boost my confidence, I still need to write the top-level test-bench module. Anyway, I'm just wondering if I need to bother worrying about this "warning." I've seen some warnings actually end up being errors in the past, so if anyone knows what's happening here, I'd be much appreciated. Thanks! Code: WARNING:Pack:1543 - The register busctl/c_oe has the property IOB=TRUE, but was
not packed into the input side of an I/O component. The register symbol "busctl/c_oe" has no connections inside the I/O component. |
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| Author: | Arlet [ Mon Oct 31, 2011 6:36 am ] |
| Post subject: | Re: WTH does this mean? |
kc5tja wrote: Code: WARNING:Pack:1543 - The register busctl/c_oe has the property IOB=TRUE, but was not packed into the input side of an I/O component. The register symbol "busctl/c_oe" has no connections inside the I/O component. IOB=TRUE means that the register should be mapped onto the specific flip flop that's inside the I/O block at the edge of the FPGA, where the actual I/O pad is, instead of an arbitrary flip flop somewhere in the middle. You're probably getting the warning because you don't have a UCF file yet, and therefore the actual mapping can't be done yet. |
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| Author: | kc5tja [ Wed Nov 02, 2011 8:07 am ] |
| Post subject: | |
Awesome -- that's the confirmation of suspicion I was looking for. Thanks.
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