I know a plurality of PS/2 adapters exist for a wide variety of CPLDs and FPGAs. However, I've never seen one that really met my needs in terms of ease of programming, flexibility, and reduced memory footprint. Add to that the fact that most PS/2 interfaces seem to depend on a host processor's interrupt handling facilities, and you can see why I found existing PS/2 interface solutions unworthy of my attention.

I decided to design my own keyboard/mouse interface, one which did not depend on a host microcontroller being implemented, didn't depend on the availability of interrupts (the J1 CPU I'm using lacks them), and had a very small I/O memory footprint. You can see the data sheet here:

https://bitbucket.org/kc5tja/kestrel/sr ... asheet.txt

Feel free to navigate around the repo to see other Verilog modules. At the time I am writing this, the PS/2 deserializer has been implemented in Verilog. I am still working on the FIFO and processor interfaces.

The "processor interface" conforms to the Wishbone bus specification, for greatest applicability to other projects and cores.

Oh, what does UXA mean? Well, between the VGA interface and the two PS/2 interface instances, plus perhaps an audio interface, it's clear that the I/O modules I'm writing all work together to establish a user experience. Hence, UXA is the "User Experience Adapter."

The PS/2 interface logic is complete.