I agree, if I first read "6502 Multi-Core..", I would've thought that too.
Arlet wrote:
How are you producing the graphics ? I didn't see a VGA module on your list, and I didn't really understand the reference to PS2 with respect to the graphics software...
No VGA core, yet. I really wanted to keep everything moderately simple. Simple is fast. Besides connecting multiple I/O cores onto an FPGA, one of the main goals is to see top speed of your CPU design. Although, after refreshing my memory, and rereading BigEd's post after you added BCD mode
here, I see the expected speed @~54MHz. That will go perfectly with the SSD1963, as that top speed is ~50MHz. Should make for some impressive 6502 controlled graphics methinks!
So I am relying on a hardware controlled TFT display for the video. It's a 640x480 pixel display with 18-bit color. I will have to explain abit more about the controller later, it's very nice. But for anyone interested it's an
SSD1963.
I have 2 fonts, 3x5 & C-64. I use only 16 colors, same colors as the C-64, in a lookup table. Also, there are 7 sizes. These are the character attributes.
When you type on the keyboard, you see the characters. This much I've accomplished.
I'm working on the last piece of 6502 software for my PWA project in the hardware section. It is a hex dump from a banked 2Mx8 SRAM to the display. That PWA project is going to morph into a 65816 controlled system. I'll update that thread soon as well...
But as I said, I didn't want this effort into the software to be wasted, so what better way to use a known successful chunk of software to test the 6502SoC, especially since it is already using 1 of the I/O interfaces.
Earlier I said, this could take 6 months to a year. I don't anticipate getting the 6502 core and the PS2 core "up and running" to take very long, after the wiring.
Nothing is even on paper yet, but my little mind's eye is picturing 5 IC's:
The XC3S400 Spartan 3
The FPGA PROM
A 2Mx8 SRAM
A 512Kx8 EEPROM
An I2C programmable oscillator
Here's a block diag of what I'm thinking. As in the PWA, the "OS" will be copied from slow EEPROM @F1(2.5MHz), and run from SRAM @F2(20MHz+). The 2GB SD will hold "test data". I'm thinking bitmap pic info that can be readily copied from the PC to the SD card. Then plugged into 6502SoC and outputted to the display to test the SD core.
CPU core chosen. I'll list and credit the other cores next...
edit: Added more info after, "No VGA yet,..."