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ElEctric_EyE
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PostPosted: Sat Sep 24, 2011 9:07 pm 
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Last edited by ElEctric_EyE on Thu Oct 20, 2011 6:08 pm, edited 1 time in total.

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Arlet
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PostPosted: Sun Sep 25, 2011 6:22 am 
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You don't need the ORs module at all, just get rid of that. Instead, I assume you have different modules for PS2, I2C, SPI, ROM and RAM. Each of those modules has a port with a data out bus. I assume all of those signals are named 'DO'.

What you do is declare a 'di' bus, 16 bits wide and define it as "wired OR"
Code:
wor [15:0] di;


I've called it 'di' because it's going to be the input for the CPU. Now, simply attach all your modules to this bus, as well as the CPU.

Code:
ps2 ps2( .DO(di), ... );
i2c i2c( .DO(di), ... );
rom rom( .DO(di), ... );
ram ram0( .DO(di), ... );
ram ram1( .DO(di), ... );
cpu cpu( .DI(di), ... );


Each of those modules also needs a chip select signal, and it must produce all zeros on its output bus when it's not selected. If it doesn't need the upper 8 bits of the bus, it just ties them to zero permanently. The synthesis tools will automatically insert all the necessary ORs for you.
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ElEctric_EyE
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Last edited by ElEctric_EyE on Thu Oct 20, 2011 6:08 pm, edited 1 time in total.

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Arlet
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Yes, that would be on the top level. I've never used schematic entry, but perhaps there is also a way to define a 'wor' signal in a schematic.
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ElEctric_EyE
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Last edited by ElEctric_EyE on Thu Oct 20, 2011 6:08 pm, edited 1 time in total.

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Arlet
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PostPosted: Tue Sep 27, 2011 5:41 am 
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By the way, I've pushed some fixes to the github archive of the verilog-6502. You'll need to merge those with your own forks.
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ElEctric_EyE
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Last edited by ElEctric_EyE on Thu Oct 20, 2011 6:07 pm, edited 1 time in total.

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Arlet
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PostPosted: Tue Sep 27, 2011 2:03 pm 
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You should use '|' instead of '||' for a bitwise logical OR.

You can also write it using the entire bus at the same time.
Code:
assign DO = INA | INB | INC | IND | INE | INF;


Verilog will automatically extend the IND-INF ports will additional zero bits.
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ElEctric_EyE
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Last edited by ElEctric_EyE on Thu Oct 20, 2011 6:07 pm, edited 1 time in total.

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Arlet
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PostPosted: Tue Sep 27, 2011 3:16 pm 
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You can use my UART if you want.

uart.v - the UART core
uartif.v -wrapper to attach UART to CPU

The UART core was one of my very first projects I did for the Spartan-3 board, when I was just starting to learn Verilog. I still use it whenever I need a UART interface. It's very simple and basic. It only supports 8 data bits, 1 stop bit, no parity, and a fixed baud rate. It assumes a 50 MHz clock, but you can easily change the clock frequency in the code.

The UART wrapper I wrote later, when I needed a UART in a 6502 project. It uses two memory mapped registers. One for data, and the other for control/status.
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ElEctric_EyE
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Last edited by ElEctric_EyE on Thu Oct 20, 2011 6:06 pm, edited 1 time in total.

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ElEctric_EyE
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Last edited by ElEctric_EyE on Thu Oct 20, 2011 6:06 pm, edited 1 time in total.

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Arlet
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ElEctric_EyE wrote:
Ok, That UART looks like it should work great just using the TX and RX, thanks again! Looking at your code, I see you have it set to go 115200baud. You had it sending data reliably without any use of CTS and RTS?


Yes, 115200 worked fine, but I had a form of flow control in my higher level protocol so the buffers wouldn't overflow.
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ElEctric_EyE
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Last edited by ElEctric_EyE on Thu Oct 20, 2011 6:06 pm, edited 1 time in total.

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ElEctric_EyE
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Last edited by ElEctric_EyE on Thu Oct 20, 2011 6:05 pm, edited 1 time in total.

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