Hallo allemaal,


First this question: is there a VHDL core available of the 65816? AFAIK none. (T65 is incomplete; see its own comment)

Working at my own code I wondered if there is an advantage having a mixed 8/16-bit mode for the various registers. IMHO only 8/8 and 16/16 are sufficient. I realise that sometimes you are only allowed to read/write one specific byte because reading/writing the next byte as well could cause havoc (think of reading/writing of/to registers of an IC). But I cannot imagine reading/writing data byte-wise over a bigger range then 256 bytes. This would mean that 8/8 will do. But any good argument in favour of the 8/16 is welcome!

@ André:
I haven't found anything in your specs that support a mixed mode. So IMHO it won't hurt to think about it in case someone comes with a valid reason.

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In my 65k specs the register width is determined with every opcode independently (using the prefix bytes), so there is no "mode" as such

André

OK, maybe "mode" wasn't the right word in this case. But you only provide two bits, RS0 and RS1, for the register size. So what about "LDA $1234,X"? "LDA.W $1234,X" means both (or at least A) registers are 16 bits wide. How can I tell the CPU to use the 8/16 combination?

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Ah, I see, I didn't get it the first time. The index registers are always full width. The "width" of the index register value is determined by the width of the opcodes you manipulate them with.

If you load an 8-bit value, the index register has the upper bits set to zero (see ZE prefix though...), so it's 8-bit. If you INX/INY with 8 bits width only, the index register value stays 8-bit. This takes advantage of the fact that index registers are not signed.

But you could also do:



When used in an addressing mode, the index registers are always full length. So you could

which would actually read a byte (LDA is not width-prefixed) from address $10800 (no bank boundaries)

This is exactly to avoid the double mode setting problem you asked about.

André