Another success with a 484-pin BGA. 6502 playground rev.C - works like a charm, at least flashing an LED. Power regulators and an oscillator are mounted:

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

Consistency is nice work enso!...

This is my progress so far of a top level layer board so far, without concern for other specialized pins. VIAs are powers/GNDs as mentioned before.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

You are on your way!

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

Some of the remaining signal pins could be routed to the bottom layer using more vias, but I didn't want to cloud that layout as it shows the most basic number of pins one can easily route using a 16x16 1mm BGA package on one layer.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

3-D Circuit Boards.

Now one issue that I have been trying to think about out of the box, is bypass capacitor placement. I've seen the layouts with all the bypass caps surrounding the BGA on the top layer. This can be done better IMO.

The one person who inspired me to think out of the box is Garth Wilson, with his idea on placing SMT cap's inside of a via on a 2-layer board. Today I think I figured out a feasible way to implement the same concept, although it is labor intensive, using a 2-layer board (although only the ground plane is used) which is soldered in at the last stage. There may be more uses of the other plane, But here is the process:

Manufacture a 4-layer board made with a 256-pin 1mm BGA, using power/GND vias.
Manufacture a 2-layer bypass capacitor board, same dimensions as the BGA (not the large 4-layer board) with holes drilled at same power/GND via locations. On this board, the vias will be large enough to accommodate the SMT caps. All GND vias with go straight through and connect both boards.
Solder the BGA IC to the top of the 4-layer board.
Solder the bypass caps vertically on each power via on the bottom of the 4-layer board. (this is the tough part)
Place the 2-layer bypass capacitor board on top of all the caps, and solder them in, using the smallest amount of solder, no flux.

The constraints of this idea are:
The width of the BGA power vias will limit pretty much limit the width of the bypass capacitors.
Similarly, the thickness of the bypass board limits the bypass capacitor values.
...

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Great minds think alike

A week ago I sent off a PCB order to test out the 603 cap inside a via. Unfortunately, oshpark will not do unplated vias, so I put down two pads and will drill it myself. According to oshpark, American fabs will always plate holes with pads on both sides. I found Chinese fabs that will do unplated holes though.

Having thought about it for a while, other than more compact and nicer looking design, it is easier to just keep the caps on the surface. I will report.

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

I see now from another project board I had made for the JTAG connector, the holes are plated through just like the smaller vias. Probably to help with the soldering of a connector for example. But we don't need connectors here, nor do we need mass manufacturing.
We will have to drill it ourselves.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

We are both quite mad, you know!

Golden Phoenix will do unplated holes, listed in a separate drill file.

My plan is far less ambitious than yours, E-Eye. I will stick with a two-layer board, stuff the holes with caps, and put a layer of paste over the top to hold them in. Then I will flip the board and paste over the bottom. The surface tension should keep the caps centered in the hole. This step may require using the oven. I may just do everything in the oven - after PID-controlling it.

Alternatively, the cap-stuffing part can be done in the oven, followed by the hotplate for the BGA.

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

I would experiment with the in-hole capacitors before adding the BGA. I've done quite a few of them now for my modules, and I still don't do it right every time, so I have to correct it. I go one cap at a time, and measure the VDD-GND capacitance each time, so if there's an open or a short, I don't have to wonder which one it is (since it's obviously the last one I worked on).

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Wise words. The board I ordered is for a 0.5mm QFP. Of course I want to put the caps under the chip, so the success hinges on being able to apply just enough paste to keep the cap soldered without bulging out. I will have to fine-tune the stencil to be just the right size.

Sticking caps into holes under a BGA is a whole other project... I'll see how this one goes first.

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

Here is the back view of my XC3S50 LQFP board showing the pads that will be drilled for caps:

The top layer, under the '50 is a ground plane. You can see the concentric circles of the three power supplies. This should provide clean decoupling.

The layout is certainly much neater than having all those caps sitting on the surface...

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

For a QFP package I wouldn't think bypass capacitor placement is as bad as it is for a BGA since all the power leads are at the edge. For the BGA, most of the powers originate at the center of the device while the grounds are closer to the edges. The bypass cap's I've seen on Digilent boards, for example, surround the device. Think of the length of wire needed to connect this...
In my parallel video board using a 144-pinQFP, every single one of the power lead bypass caps are <= 2mm distance from the package. I see no advantage to "burying" a bypass cap for a QFP package that is expected to run <200MHz.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Agreed, no point other than getting the details worked out with a simpler technology. The only inaccessible area is the top groundplane under the the QFP so the chances of a hard-to-diagnose failure are low.

I needed to quickly test and fine-tune the process, and the 'neatness' factor made it irresistible...

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

Very interesting. I did a test today, my lights were pulsing dimming. Erroneous reading the bare Al at 70C throughout this test, while the TC was @250C, where I had PID controller set. I used an old board with a defunct 144-pin QFP Spartan 6. It was soldered using 62/36/2 silver bearing solder, and was easily removed when the IR measured 175C. 179 is the actual M.P. Took about 10 min's to get to that temp. Moving the part of the board where the device needed to be removed directly over the heating element sped up the process. The board seems to have survived the process without any change, it had just begun starting to smoke though, this may have been the flux though, hard to tell.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

So I am eager to start production of my 3D bypass capacitor board, each .67"x.67" board will have 62 holes. Each of those holes will be a .056" via with a .029" hole. The 0605 caps will be a snug fit, since they are .065"x.032". Some things I have to consider are the number of holes per board. Max is 650 for ExpressPCB ProtoPro 2 layer service, the one that can't exceed 21sq". Which real estate is not the issue here, number of max hole is the limiting factor. So I can have multiple bypass cap boards on a single manufactured board. Looks like about 10. I will use extra holes remaing to make separation easier. $166 will get me 4x10 boards. I have to get the measurements correct the first time! I may have to go with the .065" via with the .035" hole.

The Green is usually the bottom layer, but in this case it is on top for the bypass cap board on the left. The red layer will have to be etched off, and all the VCC power holes will have to be drilled. The GNDs will have wires to go through both boards.
Ignore the error on the pic, this was just a rough draft.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502