I meant to mention that as well, thanks for bringing that up BDD!
Their software is proprietary, in order for them to make their boards for you, but as of the 1.1.6 release from Nov 2018, one now has the option to receive a Gerber file by email after ordering their boards. I think that's pretty smart.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

I just checked the design for pricing. For the 4 layer board at this stage @2.5" x 4.5" with 515 holes it's about $150. There's an Include Gerbers' checkbox, and it's doesn't affect the final price. So it is a free optional service.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Thanks for the clarification, Sam. I've used ExpressPCB a couple of times and I like their free pcb-design software but I always resented the vendor buy-in that comes with it. This new option seems like a step in the right direction, albeit it a small one. (Sounds like you're still locked in for the initial order. But if you plan on reordering the same design you could take the business elsewhere.) Hmmm... kinda makes me wish I could just buy the software in the first place.

Nice to hear about the progress on your project! Sounds like you're enjoying the work. Here's hoping the first time is the charm!

-- Jeff

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Wow, that is expensive. My daughter printed a 7"x11" four layer PCB for $80 I believe at JLCPCB

What software did she use? How much is it?

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Exactly! Possibly take the business elsewhere, maybe a house that can do IC mounting. It just gives more options from a free piece of software which seems to be only getting better IMO.

When I finally do put in this order I intend to see if they've finally got the tented/non-tented vias under control. I really wanted this project centered around 1 676-pin Xilinx S6 FPGA. All address lines, all data lines from all 4 SyncRams go into the BGA, individually... *Sigh* Maybe 1 day.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

She used KiCad, it's free. They also partner with or own EasyEDA which I think offers PCB design software ?

Yes KiCad, I'm very familiar with it. That is also a very nice piece of free software for what we're doing here...
However, the last time I used KiCad about 6 months ago, it still wants you to link eSchema to the board layout tool. I couldn't assign vias to any layer without a schematic. EPCB lets you do this manually without a schematic.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

That still hasn't changed. I have been prevented from making several stupid mistakes by that requirement. It really isn't as onerous as you're making it out to be.
I believe there are ways to get around it, but there really isn't much of a reason to.

The idea of a schematic, or netlist, is that you lay down "this is what I want to implement" and you can check that for logic and your intention, and then when you make the layout you can check it - "does this connect the way I wanted it to?" and that's pretty valuable.

At the place I worked from 1985-92, we used OrCAD, schematic first and then PCB layout guided by the schematic capture's output. We still got layout errors. I have not used schematic-capture software since I left there, and I don't get layout errors anymore either, because I use a checking system that a new engineering manager there got us started on just before I left, outlined in this post: viewtopic.php?p=17653#p17653 .

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

So the fact remains, I've been using the EPCB software because I can avoid wasted time making a schematic with IC's that number over 100-pins each... When I write the constraints file assigning FPGA pins to all the other IC's, this is just 1 more way I double check the connections.

In other news, I hit a snag with the TDA19988. The datasheet does not spec the I2C registers. I set up a case with NXP and the rep said it was basically EOL and couldn't provide any info other than some stuff regarding resolutions below 1080p. I checked a very similar device made by Analog Devices and they want you to sign an NDA to get this info. I don't think I really have a problem with this but it does mean quite abit of rerouting. Part of me is so tempted to go back to VGA...

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

I think I'm going back to using a videoDAC I used in the PVB project, which is the ADV7125. This way I stop wasting so much time on BS. Just straight video, no registers to mess and nothing proprietary. I was reading on HDMI.org, I would have to adopt something or other and IC companies go along and you have to sign an NDA and pay royalties. Screw them. There are cheap external VGA to HDMI adapters out there. So this is the way I'm proceeding videoDAC. Live and learn!

EDIT: I can't use the ADV7125 and Analog Devices doesn't make a videoDAC with 1.8V digital inputs, but TI does. Although it's not recommended for new designs, the THS8135 does what I need, triple 10-bit 220MSPS 1.8V digital inputs and 3.3V analog outputs in a 48-pin .5mm QFP package. Also, DigiKey still sells them for under $10 eaUS. The VGA connector will fit perfectly where the full size HDMI connector was. This shouldn't take too long to update the schematic.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Found a huge oversight. I missed one of the address pin connections from SyncRAM to FPGA. This happened in all 4 instances because when I had the 2 RAMs, on the top and bottom of the board wired up to the 1st FPGA, I just copied/pasted and rotated the design to speed things up.

Since things are so tight and the RAM to FPGA connections were the very first part of the layout that was completed, instead of starting from scratch, which I was seriously considering, I think a wiser option would be to go to the thinnest trace width available which is .006" for all signal traces on the board. Currently they are .010". It's going to involve quite abit of work but should reduce the chance of wiring errors. I don't think it will be done before New Years as planned but I'm glad I caught it before ordering boards. I think this qualifies as version 1.1.

Progress?

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

All signal traces are .006" and I now see a viable way to make room for the missed pins. I'll tackle this tomorrow. However, it will mean only 18 pins, instead of 19, for the FPGA-FPGA communications. Working on updating the block diagram too.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502