Just mounted a couple of 700ANs using my hotplate. Have a total of 3 now, with a problem:

Current draw: 0.8A from the 5V supply! The chip gets hot (not too hot, just hot enough to be uncomfortable to the touch). This seems just wrong...

Impact identifies the chip correctly.

With the first one, I assumed a BGA mounting issue - a short somewhere... But with 3 behaving the same way, I suspect that I did something stupid, like grounding some pins that should not be grounded...

I am very confident in my ability to solder the 484 pin BGA, at least.

Has anyone had anything like this happen?

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

Describe more exactly how you're mounting these BGA's, with pics if you can. I am interested in BGA, I will do some research and help if I can.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

My final mounting procedure is extremely simple:
-Clean board with alcohol
-Apply liquid flux
-Place the FPGA
-Heat on PID hotplate (latest setting 250C about 30sec. As the balls start melting, a slight slumping occurs)
-Visually verify. Balls have a distinct shape, and I am able to see through every row all the way to the back.

I am pretty certain that the mounting is not the problem as I have 256-pin BGAs working very well.

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

If you have the 256-pin BGA's working, I would say not only is your mounting technique solid, but also your attention to detail is excellent. There is definately something peculiar to the 484-pin Spartan 3AN device that is different than that of the 256-pin device, or else you made a board design error...

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

So your thread here is about the 484-pin? I would change your header topic to address this specific concern.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Sorry, I am having trouble fitting into the thread structure. Originally this thread was about which configuration pins need to be set for the ANs. It appears that I must've misunderstood something about the architecture and made 2 revs of PC boards that are bad. The problem has to do with the configuration pins as the rest of the pins on this board are currently not connected.

I am not entirely off-topic.

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

I agree that a soldering problem doesn't seem likely, but you could try pulling off the FPGA and analyze the damage to see how they were soldered.

Xilinx sells a Spartan 3A/3AN Starter Kit using a 484-pin XC3S700 and they have a schematic on their website.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

I may have to resort to this. I have a couple of 200ANs off the boards from previous attempts, having to do with solderpaste application.

ElectricEyE- Thanks for the schematic pointer. I will refer to it and check the wiring. These boards usually have way too many devices connected, but should be helpful anyway.

Possible explanation

Because my circuit is a 2-layer board, I routed some power and ground buses directly across unused IO pins deep inside the grid, thinking that it should not matter. At some later point I think I grounded the PUDC_B pin, enabling internal pullup resistors during configuration (I can't remember why I did this). This, of course, turnes the grounded pins and their respective pullups into little heaters.

If this is the case, the boards are actually usable since the heating is not terminal and the issue should go away after configuration, which should not take more than a few seconds.

Is the 0.8A current consumption consistent with 10-20 shorted IO pins? It seems a little high, but well within the range of possible. I am away from the circuit, will check this later today.

Edit: looking at the layout I counted 49 inner pins that are grounded by the power distribution bus. With a meter, 3.3V power grid draws approximately 730mA. That's about 15mA per pin, perfectly explaining the problem.

Next task: create a simple test circuit and configure the FPGA, which should fix the problem...

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

I created a simple test circuit that turns an LED on basted on another pin. That works fine.

Power consumption remains .8A! WTF...

I modified the UCF file with names for all the grounded pins, set them up as inputs in the 'top.v' file. Still drawing .8A ... Checked with FPGA explorer to make sure the IOBs are not optimised out - they are all there. Out of desperation, listed all pins shorted to the 3.3V bus as inputs as well, even though it makes less sense. Nope, still 0.8A, running hot.

So as far as I can tell, it works but runs in 'ungreen' mode, sucking power somewhere...

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

It's a short between VCC and VINT. Bare board shows the 2 buses as isolated, fine. The soldered version with 1.2V only shows 1.2V on the 3.3V bus, and vice versa when connected to one supply only. With both connected, VINT reads 2.9V. How did I miss it before? Will go looking for the problem.

Interestingly, connecting just VCC (that is driving VINT at 3.3V) works fine! Probably reducing the lifespan of the chip substantially, but surprisingly resilitent.

PROBLEM FOUND

Stupid every day! Pin P11 was erroneously connected to VINT instead of VAUX/VCC. It sits in the VINT checkerboard pattern, so I see why I missed it. 3 XC3S700AN chips added to the future 'reballing' box.

Thank you for your help.

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut