Some major changes have been made to the project: There used to be 3 control bits from the cpu to various modules: CB0 for page 0 or page 1. CB1 for page flipping or scrolling and CB2 for scrolling horizontal or vertical. Also at this point I was having difficulty meshing the horizontal scrolling with the vertical scrolling. Also, I was using 2 11-bit offset registers in the form of 2 Accumulator registers pulled off of the 65Org16.b core. The O accumulator adds offset in the vertical, and the N accumulator for the horizontal offset.
Now I still use those registers, but only 1 control bit for the same functions goes to the SRAM interface module, CB0 for controlling resolution to maximize the 2MBx18 video RAM usage, either CB0 = 2048x1024 or !CB0 = 1024x2048. Also, CB0 will allow the hardware line/circle generator to plot offscreen in the set direction. The appropriate offset accumulators are used to page flip and scroll by adding the desired amount. Now they should be able to scroll diagonally. This will be the end-test for successful horizontal and vertical scrolling. That is the next...
BTW, I will be updating the header over the next few weeks. A new section will be added, called the 'Captain's Stardate Log'.
Consider it an ongoing chapter reference that one can use to navigate through this long blog of a thread.
Anyway, here is my algorithm for the vertical and horizontal scrolling. I remembered finally from earlier testing (with higher priority problems present), that I had to pull the high bit out of the X for the MSb:
Code:
// optimize the SyncRAM address from the CPU for plotting.
// (X,Y) in the (LSB(byte=16bit),MSB(byte=16bit)) for indirect indexed on the 65Org16.b CPU address bus, in different plotting/scrolling modes
reg [20:0] cpuABopt;
always @*
if ( CB0 ) begin // scrolling horizontal, 2048x1024
cpuABopt [20:11] <= cpuAB [31:16] + OACCout [9:0]; //Y [9:0]
cpuABopt [10:0] <= cpuAB [10:0] + NACCout; //X [10:0]
end
else begin // scrolling vertical, 1024x2048
cpuABopt [20:10] <= cpuAB [31:16] + OACCout; //Y [10:0]
cpuABopt [9:0] <= cpuAB [9:0] + NACCout [9:0]; //X [9:0]
end
//MUX the line generator, cpu and video pixel addresses to the external SyncRAM
always @*
if ( CB0 ) SRaddr <= RAMWE ? { X1 [10] + OACCout [10], Y1 [9:0] + OACCout [9:0], X1 [9:0] + NACCout [9:0] } // horizontal
: vramCS ? cpuABopt : { X [10] + NACCout [10], Y [9:0] + OACCout [9:0], X [9:0] + NACCout [9:0] };
else SRaddr <= RAMWE ? { Y1 + OACCout, X1 [9:0] + NACCout [9:0] } // vertical
: vramCS ? cpuABopt : { Y + OACCout, X [9:0] + NACCout [9:0] };
EDIT: This is more correct, didn't need the cpuABopt register. :
Code:
//MUX the line generator, optimised-cpu and video pixel addresses to the external SyncRAM address
always @*
if ( CB0 ) SRaddr <= RAMWE ? { Y1 [9:0], X1 } // horizontal
: vramCS ? { cpuAB [25:16], cpuAB [10:0] }
: { Y + OACCout [9:0], X + NACCout };
else SRaddr <= RAMWE ? { Y1, X1 [9:0] } // vertical
: vramCS ? { cpuAB [26:16], cpuAB [9:0] }
: { Y + OACCout, X + NACCout [9:0] };
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When scrolling horizontally, the code looks at 2048 ([10:0]) x 768 ([9:0]), actually 2048x1024. When scrolling vertically the RAM arrangement is 1024 ([9:0]) x 2048 ([10:0]). I could have done what I wanted to do at this resolution with a 4M ([10:0] x [10:0]) device, but diagonal scrolling is not at the top of my list.