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| Learning Verilog or VHDL from some good books/sources? http://forum.6502.org/viewtopic.php?f=10&t=2264 |
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| Author: | BigEd [ Tue May 26, 2015 7:10 pm ] |
| Post subject: | Re: Learning Verilog or VHDL from some good books/sources? |
BigEd wrote: Another seam of resources: http://eesun.free.fr/DOC/VERILOG/synvlg.html via http://people.ece.cornell.edu/land/courses/ece5760/ (includes video lectures) Found some more: http://staff.washington.edu/jon/verilog-prog.html Which points to further works online: http://web.archive.org/web/201303280228 ... index.html (Via http://jon-jacky.github.io/home/links.html#engr-elec which has a great number of links to lots of interesting things.) |
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| Author: | Rob Finch [ Tue May 26, 2015 11:46 pm ] |
| Post subject: | Re: Learning Verilog or VHDL from some good books/sources? |
I was reading an earlier post and got confused. This issue has already been delt with. but here is an example of blocking assignment use. One cannot mix blocking and non-blocking assignments to the same reg however. A simple example bitfield extract (o1, o2 and o are calculated in a blocking manner within an always block - this is synthesized code): Code: `BFEXT:
begin for (n = 0; n < DWIDTH; n = n + 1) o1[n] = mask[n] ? a[n] : 1'b0; o2 = o1 >> mb; for (n = 0; n < DWIDTH; n = n + 1) o[n] = n > ml ? o2[ml] : o2[n]; end |
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