Too tired for further testing today, but here is the software I use to copy the character from external videoRAM and paste that data right next to the original. The original character is written by a separate PLTCHR software routine.... The indirect W comes into play here for an easy time with copy/pasting indirect indexed style, which is needed since the LSB is the X, and the MSB is the Y in the HVSYNC generator. This is .b core compatible BTW...
Code:
LDA #$00
STA SCRHI ;y position
STA SCRLO ;x position
LDX #$08 ;use X reg for easy test for end of y position
CHSH2 LDY #$00
LDWi $0008 ;LDW #$0008
CHSH LDA (SCRLO),Y
STAiw (SCRLO),W ;STA (SCRLO),W
INW
INY
CPY #$0008
BNE CHSH
INC SCRHI
DEX
BNE CHSH2
Also, my interface module has changed (never got around to the state machine!!!), sorry for the lack of comments. Also this module is still separate from the HVSYNC generator, so the bidirectional bus to/from the external video SyncRAM appears to be successfully routed to 2 modules. 1 read only, 1 read/write:
Code:
module SRAMif( input clk,
input [15:0] cpuDO,
input vramCS, //cpu is reading/writing to videoRAM
input cpuWE,
input RAMWE, //LineGen is drawing
input CB0, //Control Bit 0 from cpu to control page 0 or 1, when page flipping
input CB1, //Control Bit 1 from cpu to control page flipping or scrolling
input CB2, //Control Bit 2 scrolling horizontal or vertical
inout [15:0] SRD,
input [15:0] QACCout, //pixel color from cpu
input [9:0] X, //LSB of LineGen address
input [9:0] Y, //MSB
input [20:0] Vaddr, //pixel clock address from HVSync Generator
input [31:0] cpuAB,
output reg [20:0] SRaddr,
output reg [15:0] SRDO, //to cpu
output reg SRWEn
);
reg [15:0] SRDI;
reg SRWEn2;
always @(posedge clk) begin
SRWEn2 <= SRWEn;
if (RAMWE && !vramCS) begin
SRDO <= 16'h0000;
SRDI <= QACCout;
end
if (!RAMWE && (vramCS && cpuWE)) begin
SRDO <= 16'h0000;
SRDI <= cpuDO;
end
if (RAMWE && (vramCS && cpuWE)) begin
SRDO <= 16'h0000;
SRDI <= QACCout;
end
if (!RAMWE && (vramCS && !cpuWE)) begin //reading from RAM
SRDI <= 16'hZZZZ;
SRDO <= SRD;
end
else SRDO <= 16'h0000;
end
reg [20:0] cpuABopt;
always @* //optimize the videoRAM address for plotting (X,Y) in the (LSB,MSB) for indirect indexed
begin //CB1 = 0, page flipping
cpuABopt [20] <= CB0; //bank bit
cpuABopt [19:10] <= cpuAB [31:16]; //Y[9:0]
cpuABopt [9:0] <= cpuAB [15:0]; //X[9:0]
SRaddr <= RAMWE ? { CB0, Y, X } : vramCS ? cpuABopt : Vaddr;
SRWEn <= !(RAMWE || (vramCS && cpuWE)); //0 = write to RAM
end
assign SRD = SRWEn2 ? 16'hZZZZ : SRDI; //I/O MUX'd latch to SyncRAM databus. High 'Z' during a read
endmodule
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