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PostPosted: Wed May 15, 2013 5:03 pm 
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I fixed the issue I had with aligning the bits of the X/Y video pixel counters with the cpu accessing the videoRAM. The vertical scrolling works correctly, but there is a problem with the horizontal scrolling. I suspect it has something to do with me using the O and N accum ulator values which are not in sync with the video timing. I'll try to use programmable counters next attempt. This video shows what is currently happening, and I will explain:

VIDEO

1) Page 0 (1024x1024) of video (1024x768) is filled with black pixels. The remaining 'uncleared' pixels (1024x256) can be seen underneath.
2) Then a circle with diameter 239 (1/2 vertical = largest circle) pixels is plotted with green pixels.
3) Page 1 of video is filled with blue pixels. Again the remaining uncleared pixels can be seen underneath.
4) Then a circle with diameter 119 pixels is plotted with yellow pixels.
5) Page 0 is displayed first and vertically scrolled (1024x) upwards into Page 1, then back into Page 0
6) Then Page 0 is horizontally scrolled (eventually) into Page 1 (1024x), but this is where it is not working properly. I suspect the software delays have something to do with the improper timing.
7) Then Page 0 is 'flipped' back to the display, and the radar sweep using LineGen is seen.
8) Repeat to step 1

The software is not too terribly long, so I will post so any interested can see what's going on:
Code:
;-------------------------------------------------------------------------------
                                          ;CB0 : PAGE FLIP CONTROL
                                          ;CB1 : 1 = SCROLL, 0 = PAGE FLIP
                                          ;CB2 : 1 = SCROLL HORIZONTAL, 0 = VERTICAL
                                          ;CB3 : TBD - to be determined
                                          ;CF0 : 1 = LINE GENERATOR READY, 0 = NOT READY
                                          ;CF1 : 1 = VSYNC IS IN RETRACE, 0 = ACTIVE DISPLAY
                                          ;CF2 : 1 = HBLANK, 0 = ACTIVE DISPLAY
                                          ;CF3 : TBD
                                          ;Processor Status P = { 16'b0, CF3, CF2, CF1, CF0, CB3, CB2, CB1, CB0, N, V, 3'b110, I, Z, C };
START:            LDA #$1000             
                  TAZP                    ;SET ZEROPAGE @$1000_0000
                  LDA #$1001
                      TASP                    ;SET STACKPAGE @$1001_0000
                                          ;
                  CCB0                    ;0 = VIDEO PAGE 0, 1 = VIDEO PAGE 1
                  CCB1                    ;0 = PAGE FLIPPING, 1 = SCROLLING
                  CCB2                    ;0 = VERTICAL, 1 = HORIZONTAL
                 
                  LDX #0                  ;SET BLACK SCREEN ACCORDING TO COLOR LUT
                  LDQax CLUT,X            ;-LDQ CLUT,X. USE Q ACCUMULATOR FOR PIXEL COLOR
                  JSR CLRSCR
                  ;LDA #%1000011100000000  ;C64 FONT, YELLOW
                  ;STA ATTBUT              ;FOR CHARACTERS ONLY
                                                     
                  LDX #5
                  LDQax CLUT,X            ;-LDQ CLUT,X. SET PIXEL COLOR GREEN
                  LDWi $017F              ;MAX RADIUS = 239
                  LDGi $01FF              ;G ACC IS XCENTER
                  LDHi $017F              ;H ACC IS YCENTER
                  STWzp RA
                  JSR CIRCLE
                 
                  SCB0                    ;VIDEO PAGE 1
                  LDX #6                  ;SET BLUE SCREEN ACCORDING TO COLOR LUT
                  LDQax CLUT,X            ;-LDQ CLUT,X. USE Q ACCUMULATOR FOR PIXEL COLOR
                  JSR CLRSCR
                 
                  LDX #7
                  LDQax CLUT,X            ;-LDQ CLUT,X. SET PIXEL COLOR YELLOW
                  LDWi $00BF              ;RADIUS = 119
                  LDGi $01FF              ;G ACC IS XCENTER
                  LDHi $017F              ;H ACC IS YCENTER
                  STWzp RA
                  JSR CIRCLE
                 
                  CCB0                    ;VIDEO PAGE 0
                  SCB1                    ;SET SCROLL
                  CCB2                    ;VERTICAL SCROLL
                 
                  LDOi $0000              ;Y SCROLL OFFSET
                  LDNi $0000              ;X SCROLL OFFSET
                 
VSCRL             JSR DELAY               
                  JSR DELAY
                  JSR DELAY
                  INCO                    ; SCROLL UPWARDS
                  CMPOi $0400
                  BNE VSCRL
                 
                  LDOi $0000
                 
                  CCB0                    ;VIDEO PAGE 0
                  SCB1                    ;SCROLL MODE
                  SCB2                    ;HORIZONTAL SCROLL
                 
HSCRL             JSR DELAY               ;SCROLL LEFT
                  JSR DELAY
                  JSR DELAY
                  INCN
                  CMPNi $0400
                  BNE HSCRL
                 
                 
                  CCB0                    ;VIDEO PAGE 0
                  CCB1                    ;PAGE FLIP MODE
                  CCB2                    ;VERTICAL SCROLL - DOESN'T MATTER
                 
                  ;line plotting begins here
                  ;LineGen module auto plots after it receives a value in 'ly1'
                 
                  LDX #3                  ;CYAN
                  LDQax CLUT
                  LDY #0
QUADRANT1         LDA #512
                  STA lx0
                  LDA #384
                  STA ly0
                  STY lx1
                  LDA #0
                  STA ly1
                  BCF0C $FFFE              ;CF0 = LineGen Ready. 1 = ready.
                  JSR DELAY
                  INY
                  CPY #1023
                  BNE QUADRANT1
                 
                  LDY #0
QUADRANT2         LDA #512
                  STA lx0
                  LDA #384
                  STA ly0
                  LDA #1023
                  STA lx1
                  STY ly1
                  BCF0C $FFFE              ;CF0 = LineGen Ready. 1 = ready
                  JSR DELAY
                  INY
                  CPY #767
                  BNE QUADRANT2
                 
                  LDY #1023
QUADRANT3         LDA #512
                  STA lx0
                  LDA #384
                  STA ly0
                  STY lx1
                  LDA #767
                  STA ly1
                  BCF0C $FFFE              ;CF0 = LineGen Ready. 1 = ready
                  JSR DELAY
                  DEY
                  BNE QUADRANT3
                 
                  LDY #767               
QUADRANT4         LDA #512
                  STA lx0
                  LDA #384
                  STA ly0
                  LDA #0
                  STA lx1
                  STY ly1
                  BCF0C $FFFE              ;CF0 = LineGen Ready. 1 = ready                 
                  JSR DELAY
                  DEY
                  BNE QUADRANT4
                 
ENDALL            JMP START

DELAY             LDWi $3FFF
GHI               DEW
                  BNE GHI
                  RTS

This is what I've been wrestling with in the Verilog HVSync module:
Code:
//pixel counters & video address
reg [10:0] X = 0;
reg [10:0] Y = 0;

always @(posedge clk) begin
   if ( hstart )
      countflag <= 1;
   if ( hblank )
      countflag <= 0;
end
         
always @(posedge clk)
   if ( vstart | (X == 1023 + NACCout && Y == 767 + OACCout)) begin
      X <= NACCout;
      Y <= OACCout;
   end
      else if ( X == 1023 + NACCout ) begin
         Y <= Y + 1;
         X <= NACCout;
      end
         else if ( countflag )
            X <= X + 1;
            
always @*
   if (CB1) begin                                                     //CB1 = 1 when scrolling, 0 when bank switch
      if (CB2)   Vaddr [20:0] <= { X[10] + NACCout[10], Y[9:0], X[9:0] + NACCout[9:0] };   //scrolling horizontal
         else  Vaddr [20:0] <= { Y + OACCout, X[9:0] };               //scrolling vertical
   end
      else       Vaddr [20:0] <= { CB0, Y[9:0], X[9:0] };            //bank switching
 


I will upload the new video shortly. Thanks for watching!

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PostPosted: Wed May 15, 2013 7:00 pm 
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I'm a bit confused now: this is a 16-bit CPU, so in what sense do you have a 32-bit PSW? Can you access it as such or are the upper 16 bits really a separate register (to the programmer)?


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PostPosted: Wed May 15, 2013 8:00 pm 
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BigEd wrote:
... so in what sense do you have a 32-bit PSW? Can you access it as such or are the upper 16 bits really a separate register (to the programmer)?

I've not tried to access the upper 16 bits yet. But in the .d core you can see what is happening with the upper 8 bits in the lower 16 bits of the P reg. I don't see a problem with expanding the P reg to 32 bits.

EDIT: There is no additional register. Each additional bit has 2 opcodes to set or clear if it is an output. And each input bit has a branch on set and branch on clear opcode.

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PostPosted: Fri May 17, 2013 1:45 am 
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Arlet wrote:
I would put the double buffering in the VGA module. All you need is a register that contains the start address of the frame in memory. The CPU can then write to this address during the vertical blank. That way, you can also implement triple buffering, or just have a single buffer, or do hardware scrolling.

Italics are my addition to Arlet's quote... I suspect this is where I've been going wrong regarding my attempt at scrolling. I've been writing the effective address 'whenever'. I've not been checking for VSYNC. I've wondered why the display scrolls up when I was adding a value to the Y pixel counter. This should have made it scroll down, since Y increases at the end of every scanline. So what I was observing was an aliasing effect, I think the effect is called aliasing. Like when you see a rotating wheel spinning clockwise in flourescent lighting powered by 60Hz, and at a certain RPM it looks like the wheel is spinning backwards... Anyway, I will try this tonight and hopefully finish the vertical or horizontal scrolling. Diagonal scrolling (i.e. vertical and diagonal) will be an interesting investigation into memory usage, I think.

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PostPosted: Tue May 21, 2013 4:38 pm 
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Man was I lost, heh. :lol: The scrolling is up because the counter is peering deeper into memory....

I finally got it working. Had to slow the scrolling way down to spot the issues, and they have all been corrected. I was trying to add in the offset to the pixel counter reset logic which was incorrect. Also, the horizontal scroll was quite a challenge! I had to swap the X and Y and re-originate the Y for an image not to be mirrored. Now the (0,0) origin for horizontal scrolling is at the bottom left of the screen.

I also added a MUX for the data out to the RAM, so LineGen can have a pixel color value of the Q accumulator, and the cpu can have any pixel color it wants when it selects the RAM. I had chosen to plot characters at all corners of the screen in order to check out the correctness of the scrolling.

Here's a code snippet from the HVSync module controlling the 10-bit pixel counters, and 11-bit offset addresses:
Code:
reg [9:0] X = 0;
reg [9:0] Y = 0;
         
always @(posedge clk) begin
   if ( vsync || ( X == 1023 && Y == 767 )) begin
         X <= 0;
         Y <= 0;
   end
   if ( X == 1023 ) begin
         Y <= Y + 1;
         X <= 0;
   end
         else if ( countflag )
            X <= X + 1;
end
            
always @*
   if (CB1) begin                                                   //CB1 = 1 when scrolling, 0 when bank switch
      if (CB2)   Vaddr [20:0] <= { X + NACCout, 10'd768 - Y };      //scrolling horizontal
           else  Vaddr [20:0] <= { Y + OACCout, X };                //scrolling vertical
   end
      else       Vaddr [20:0] <= { CB0, Y, X };                        //bank switching


There are a couple things on my agenda next:
1) Test Read/Modify/Write to videoRAM.
2) Make Verilog modules for hardware circle and hardware clear screen and merge them with the Line Generator module. The module will be renamed at this point. :roll:
3) Figure out a way to plot a circle in FPGA block memory, then skew the X and Y outputs to videoRAM to form horizontal, vertical and diagonal ellipses and partial arcs. I had seen the diagonal ellipse effect in my great many failed attempts at scrolling the circle.

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Last edited by ElEctric_EyE on Wed May 22, 2013 6:52 pm, edited 1 time in total.

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PostPosted: Tue May 21, 2013 6:54 pm 
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ElEctric_EyE wrote:
...There are a couple things on my agenda next:
1) Test Read/Modify/Write to videoRAM.
2) Make Verilog modules for hardware circle and hardware clear screen and merge them with the Line Generator module. The module will have to be renamed at this point. :roll:
3) Figure out a way to plot a circle in FPGA block memory, then skew the X and Y outputs to videoRAM to form horizontal, vertical and diagonal ellipses and partial arcs. I had seen the diagonal ellipse effect in my great many failed attempts at scrolling the circle.

I added back in the pseudo- Random Number Generator module. Previously, I had to remove it since it hampered 100MHz cpu operation. Now, since cpu and video are running at 70MHz it should be a useful tool for testing an isolated system such as this. Note that when this board is complete, it will receive commands from a 65xx type system, utilizing an 8-bit hi-speed databus, and most probably will be back in the 100MHz range, or faster.

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Last edited by ElEctric_EyE on Wed May 22, 2013 6:54 pm, edited 1 time in total.

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PostPosted: Tue May 21, 2013 10:11 pm 
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I'm starting to realize it would be quite convenient to have 1024x1024 resolution. IIRC, one of the Amiga's had this, and a special monitor as well. I dont need the monitor but the video timings would be nice. I've searched the net but couldn't find any. The only other way I know is to incrementally adjust video timings, but it's a PITA.

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PostPosted: Sat May 25, 2013 1:29 am 
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To achieve 1024x1024, I was thinking I can run a modified 1280x1024 setup which would run the pixel clock at the same 108MHz. This is within the range of the 133MHz videoRAM, and I've successfully run the project at this speed before when the .b core was capable of it. The .d core is not currently capable of this speed and I am not as hell-bent as I used to be at running a cpu softcore @100MHz.

This would mean a wider non-display area horizontally vs. vertically, something the cpu can take advantage of but probably won't be "normal" looking. I'm unsure if pixels would still be square, i.e. circles would be truly round. I will have to find out. Also, I'll have to see if the cpu system can run at 1/2pixel clock @54MHz.

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PostPosted: Tue May 28, 2013 6:17 am 
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A short update:
- The board successfully displays an output to an older style CRT monitor (same one I've been using) at 1024x1024 at 108MHz with modified timings for 1280x1024.
- The .d core cpu drops pixels running at half speed of the SRAM and HVSYNC modules.
- So the cpu will need to get back up to 100MHz speed. I will have to revert back to an older project file where the resolution was 640x480 with pixel clock @25MHz and the .b core was @4x pixel rate and slowly bring the project up to par, losing whatever .d core additions that slow it down. But first change res to 1024x1024.
- Instead of tapping the cpu core to read bits from the HVSYNC and LineGen video generators, the state machines can be forced to do this to achieve the same result with a loss of some programming freedom.

EDIT: I'm done flip-flopping! I've committed to 1024x768 as the final resolution at this stage. To regress to the .b core is simply too much work to go in the opposite direction just in the name of scrolling. Today I tried reading from the videoRAM, unsuccessful. My focus now will be on a new state machine for I/O to the videoRAM.

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PostPosted: Tue Jun 04, 2013 3:13 pm 
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Still focusing on reading from the SyncRAM. From way back on page 19 when I was first attempting to read:

Arlet wrote:
ElEctric_EyE wrote:
I sort of gave up on the IODELAY since I couldn't figure it out.

I had a hard time with it too, trying to instantiate the verilog code, but then I tried the core generator wizard, and it actually made a working design pretty quickly. I hand edited that, because it put in an extra register at the input side, which I didn't need. After experimenting with different delays, I ended up taking out the IODELAY again.

Anyway, I kept the code, so if you ever need delayed I/O, let me know.

I think I may need a peek of your code, since according to ISim, timings appear to be correct for writing and reading. I couldn't find any delay functions in Core Generator either. I'm missing it.

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PostPosted: Tue Jun 04, 2013 5:23 pm 
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Do you have your SyncRAM modelled in ISim ? If so, did you add a signal delay in your simulation ?

Anyway, here is the delay module, and this how I used it:
Code:
reg [7:0] md_out;       // output data bus
wire [7:0] md_in;       // delayed input data bus

selectio_if_wiz_v3_1 #(
    .sys_w(8),
    .dev_w(8)
)
delay (
    .DATA_TO_AND_FROM_PINS(md),
    .DATA_IN_TO_DEVICE(md_in),
    .DATA_OUT_FROM_DEVICE(md_out),
    .TRISTATE_OUTPUT(mwe),
    .CLK_IN(clk),
    .IO_RESET(1'b0)
);

Of course, the problem with interfacing external RAM is that there's a propagation delay from the RAM to the input flip flops of the FPGA. The IODELAY doesn't get rid of that, it only adds more delay. The purpose of this extra delay is to align the incoming data with a later clock cycle. So, you always need to wait an extra clock cycle before you grab the data. In the case of my SRAM, I could avoid the IODELAY because the propagation delay was already close enough to a full cycle.


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PostPosted: Tue Jun 04, 2013 7:40 pm 
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Thanks Arlet...
What are your thoughts on why it was easier to interface the FPGA for writing to external RAM vs. reading from it? I tried following the SyncRAM datasheet for the waveforms, but reading is proving to be an exhaustive effort. This RAM is rated @133MHz, I am running the entire system @70MHz pixel clock. It doesn't make sense to me why any kind of intrinsic IC delays would have more an effect on reading vs. writing.

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PostPosted: Wed Jun 05, 2013 5:18 am 
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When you're writing, the delays on the address/data/control signals are all going to be the same, since they go in the same direction. So, the edges still arrive at the SRAM device at the same time. When you're reading, you actually deal with the round trip delay from address/control -> RAM -> data.


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PostPosted: Wed Jun 05, 2013 11:21 am 
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The SyncRAM I'm using 'hides' the delay by dealing with the data 1 cycle after it sees the Chip Select, R/W, Address. I'm thinking maybe something else is going on.
I did notice one thing that may be causing a problem, not sure: I have the 'inout' data bus for the RAM in the top_level and in my RAM interface module, however I have the same bus spec'd as 'in' for the VGA module, since it is read only. Do you think maybe this is confusing ISE? Maybe I should make them both 1 module. I think you had mentioned this before....

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PostPosted: Thu Jun 06, 2013 5:31 am 
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I'm not sure how ISE would interpret that. I do think merging them in one module would be a good idea.

Have you tried reducing the clock ? You could try running the design at 10 MHz and see if that works better. At 10 MHz, the propagation delays would be small enough to meet setup times, so you can focus on functional correctness.


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