Yay it works! I confess I did not start on the state machine, it just seems too simple of a thing for a state machine. So far I have just writing to the RAM down 100% now. I did skew the clock going to the SyncRAM to make up for the FPGA delay. Maybe it's cheating, but it works! I lowered the speed of the cpu to 50MHz so I wouldn't be slowed down by running smartexplorer all the time.
It successfully clears the screen blue in software (can probably do this in hardware now), cpu sends coordinates to LineGen and is delayed a set amount, LineGen draws a red line, then the cpu draws a yellow circle.
Here is the simple interface code:
Code:
module SRAMif( input clk,
input vramCS, //cpu is reading/writing to videoRAM
input cpuWE,
input RAMWE, //LineGen is drawing
inout [15:0] SRD,
input [15:0] BACCout, //pixel color from cpu
input [9:0] X, //LSB of LineGen address
input [8:0] Y, //MSB
input [20:0] Vaddr, //pixel clock address from HVSync Generator
input [31:0] cpuAB,
output reg [20:0] SRaddr,
//output reg [15:0] SRDO, //to cpu
output reg SRWEn
);
reg SRWEn2;
reg [15:0] SRDO;
always @(posedge clk) begin
SRWEn2 <= SRWEn;
SRaddr <= RAMWE ? {2'b00, Y, X} : vramCS ? cpuABopt : Vaddr;
SRWEn <= !(RAMWE || (vramCS && cpuWE));
if (SRWEn)
SRDO <= BACCout;
end
reg [20:0] cpuABopt;
always @* begin //optimize the videoRAM address for plotting (X,Y) in the (LSB,MSB) for indirect indexed
cpuABopt [20:19] <= 2'b00; //bank bits
cpuABopt [18:10] <= cpuAB [24:16]; //Y[8:0]
cpuABopt [9:0] <= cpuAB [9:0]; //X[9:0]
end
assign SRD = SRWEn2 ? 16'hZZZZ : SRDO; //I/O MUX'd latch to SyncRAM databus. High 'Z' during a read
endmodule
I think the next logical step is to add a 'Done' bit to the LineGen module and send it to one of the cpu flags.
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