I had an 'OR's module in my project....
Now I see how to use the 'wor' on the 'top-level' for the cpu data in bus.
Another Thanks!

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Here is my testing and programming setup for now:

Power reg board (I am only using the 3.3V output) is on the left; above right is the USB-serial board. Note that the CHOCHI board has no connectors soldered - the board is fitted over a pin header on the plugboard. I find that I can fit the CHOCHI over the pin header and tilt it a little to make solid (but temporary) connections, long enough to program the flash and test the board.

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

EhBASIC is now running. Check http://apple2.x10.mx/CHOCHI/ for software and updates.

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

Great. This link shows all the sections in a reasonable order:
http://apple2.x10.mx/CHOCHI/#Summary%20 ... Bitstreams

I don't see any status reg for the serial ports: is there any indication when it has an input byte ready, or when it is OK to write another output byte?

(I'd certainly buy one or two if it ran from a 5V supply, such as I can extract from USB. Doesn't have to be a micro USB connector, although that's quite handy in EU where almost all phone chargers use it. The Raspberry Pi has a micro USB socket purely for power. Hmm, maybe I could use a Pi as a source of power as well as being the serial port master...)

I do like the idea of putting the loader down into the first two pages.

Did you keep the I/O at C000 or did you succeed in moving it down to 0200? I quite like the idea of putting it well out of the way. Putting it up in FF00 or even FFF0 is also appealling, for the same reasons.

Cheers
Ed

The serial port registers are documented here: http://apple2.x10.mx/CHOCHI/#SerialPort. I will add links to make it more obvious.

The next revision (boards are being fabbed) has a mini-USB connector and a 3.3V regulator for power. I left a prototyping area nearby and connected the USB signal pins in case anyone wants to mess with it.

I haven't moved the IO area yet. I like it in page 2 but it conflicts with EhBASIC. And keeping it high up creates a problem with ROM-like code that spans from the vectors down (Daryl's monitor being one)... It's a subject of much annoyance for me.

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

EhBASIC can be easily fixed to allow for IO in Page 2. Let me know if you want some pointers.

Daryl

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Please visit my website -> https://sbc.rictor.org/

I do indeed want pointers. It appears that EhBASIC actually uses page 2, so I didn't bother messing with it. Thank you!

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

New bitstream release - see http://apple2.x10.mx/CHOCHI/#Bitstreams

Loader now in page 0. IO still in C0xx. Cleaned up decoding - BRAMS at page 0,1,$FE and $FF (no mirroring anymore).

Please update your CHOCHI boards. Some software http://apple2.x10.mx/CHOCHI/#Software will not load without the update (old bitstreams could not load software into pages above $F8 cleanly).

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

I cut this from the v2.22 source:



On my system, $02xx was the EhBASIC buffer, $03xx was the SBC2OS buffer, and $04xx was the start of user RAM.

Change ccflag to $0300
Make sure Ram_base is set to $0400,or $0500 if you want/need some extra buffer space at $04xx.
Make sure Ram_top is correct for your sytem

This will free up Page 2.

Hope that helps!

Daryl

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Please visit my website -> https://sbc.rictor.org/

Have you posted your .ucf file somewhere ?

Here is the .ucf file for CHOCHI-B/DILDAR-X1

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

Looking at some SRAM pins with the scope, I noticed intermediate voltage levels. Looks like colliding bus drivers. Any idea ?

(I didn't update the bitstream, so it's still with the default that you programmed it with)

Hmm. That should not be the case (My apologies - I thought I'd tested your board)... The new bitstream should not be different as far as the SRAM goes, so the first thing I would do is update it and try FIG-FORTH and EhBASIC - most SRAM issues will make them not work right away.

Here is the verilog for the hardware of the new bitstream (003):

I will post a RAM test that checks all address lines tomorrow. I should really include it into the bootcode...

What pins showed weird voltages?

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

This is what I see on pin 7 (D2) of the SRAM chip.

Weird. When I touch the data pins with my finger while measuring the signal,I get strange distortions in the waveform. Doesn't look like bus collisions, but rather some high impedance signal from the FPGA, so there's a good chance the effect is benign.