Did some testing on an older CRT manufactured in 1998, unsure if it has the multi-sync hardware built in. There were vertical borders present, clearly seen about 1/2" on top and bottom. Also, bars like the ones on the right side of the above pic (flat screen monitor), were on both sides of this monitor. So the observation seems to be inline with some of my readings, that the newer flat screen monitors automatically trim HSYNC and VSYNC timings so that there are practically no visible borders.
I changed my code by memory from what Arlet had mentioned before. I thought he had used hblank as the trigger, but I saw he chose countflag. Maybe it doesn't matter? But it works. Interesting thing though, the picture is much brighter than before. I will add the 75ohm load resistors back to the videoDAC RGB outputs.
So this means I will have 1 more global clock pin freed up on v.1.0h, since I can just tie the videoDAC Blank pin high. EDIT: I think this pin will best be used for a separate MicroSD adapter serial clock apart from the serial clock common to the FLASHs.
Code:
module SRAMif( output reg [20:0] SRAddr = 0,
output reg WEn = 1,
output reg SRCS = 1,
input [15:0] SRD,
output reg [4:0] Red_data,
output reg [5:0] Green_data,
output reg [4:0] Blue_data,
output reg DACBLANKn = 1,
input clk50,
input pclk,
input hstart,
input vstart,
input hblank
);
reg [15:0] SRDtemp;
reg countflag;
always @(posedge clk50)
if ( pclk )
if ( hstart )
countflag <= 1; //countflag active in display area
else if ( hblank )
countflag <= 0;
always @(posedge clk50)
if ( vstart ) //reset address counter at top left of screen
SRAddr <= 0;
else if ( countflag )
SRAddr <= SRAddr + 1; //increment RAM address counter
always @(posedge clk50)
if ( pclk & countflag )
begin
SRDtemp <= SRD; //latch incoming data;
Red_data <= hblank ? 0 : SRDtemp [15:11]; //outgoing data to videoDAC
Green_data <= hblank ? 0 : SRDtemp [10:5];
Blue_data <= hblank ? 0 : SRDtemp [4:0];
end
endmodule
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