Added a
random number generator. So far it's only being used for the color look up table for plotting pixels. So the pic above is now made of randomized pixels. Also, in a separate experiment, I made it so each concentric circle had its own color as I was originally trying to perform a filled-in circle.
The idea now is to use the RNG to plot many circles, each with a random radius, position and color as fast as 65Org16 machinely possible.
Also, I've been working on a simple start/stop counter based on the 100MHz clock to quantify testing. I already think I know which one will be the highest speed, so I will concentrate first on the accuracy of the timer, then on that conversion to 65Org16 on my next 2 days off.
I have my timer circuit almost done in Verilog. 2 things left for the timer, then to plot characters utilizing the new plotting setup using indirect indexed. This way I'll be able to plot the timing results, I will need text!
I decided to post the code now, even though the reset bit isn't working on the counter yet...just in case anyone sees a better way of an overall Timer construction! I'm thinking this Timer is using too many resources.
I use extremely loose address decoding in order to save FPGA resources.
Code:
`timescale 1ns / 1ps
module Timer(input clk,
input [15:0] cpuDO, //cpu databus out
input cpuWE, //cpu write, active high
input cntrCS, //active high from $c000_0000-$cfff_ffff
output reg [15:0] countDO //from count [15:0] to cpuDataIn
);
reg [19:0] counter = 0; //main .01sec counter from 100MHz clock
reg [4:0] seconds = 0; //up to 32 seconds
reg [3:0] tens = 0; //10 tenths
reg [6:0] hundreds = 0; //100 hundredths
wire [15:0] count;
reg stp = 0; //control bit for stop
reg res = 0; //control bit for reset main .01sec counter
assign count [15:0] = {seconds,tens,hundreds}; //assign the bit values when reading the counter
always @(posedge clk)
if(cntrCS) begin
if(cpuWE) begin
res <= cpuDO [15]; //write to $c000_0000, bit 15 = reset
stp <= cpuDO [14]; //write to $c000_0000, bit 14 = stop
end
else
countDO <= count; //read from $c000_0000 16-bit count {sec,tens,hundreds} = xxxxx_xxxx_xxxxxxx
end
else countDO <= 16'h0000;
always @(posedge clk) begin
if (res)
counter <= 20'b0000_0000_0000_0000_0000;
if (tens == 4'b1001) begin
tens <= 4'b0000;
seconds <= seconds + 1;
end
else if (hundreds == 7'b110_0011) begin
hundreds <= 7'b0000000;
tens <= tens + 1;
end
if (stp)
counter <= counter;
else if (counter >= 20'b1111_0100_0010_0011_1111) begin //0 to 999,999 for .01sec counter
counter <= 20'b0000_0000_0000_0000_0000;
hundreds <= hundreds + 1;
end
else
counter <= counter + 1;
end
endmodule
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