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BigDumbDinosaur

Post subject: Re: A/V SBC with Multiple 65xxx CPUs

Posted: Fri Feb 14, 2020 1:17 am

Joined: Thu May 28, 2009 9:46 pm
Posts: 8504
Location: Midwestern USA

Dr Jefyll wrote:

Years ago a young fella I know was having difficulty with some troubleshooting, and I asked him whether he had scoped the power supply. He was like, why would you wanna scope the power supply? Umm... to make sure things really are as boring as you obviously assume them to be... ?

That's analogous to checking to see if your car is out of gas before tearing apart the engine to figure out why it isn't running.

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x86? We ain't got no x86. We don't NEED no stinking x86!

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ElEctric_EyE

Post subject: Re: A/V SBC with Multiple 65xxx CPUs

Posted: Fri Feb 14, 2020 10:12 pm

Joined: Mon Mar 02, 2009 7:27 pm
Posts: 3258
Location: NC, USA

I remember when I was introduced to oscilloscopes and always wondered if they could 'handle' straight DC voltages, especially higher voltages. I guess it's a stumbling block for some people, thinking that it might somehow damage a 'scope. It's critical to check the voltage rails, especially during heavy activity, which I'm nowhere near yet but instinct always tells me to check them when there's some kind of strange problem. And I mean check each IC if you're not using a power plane. Especially, if you use wirewrap or breadboard!

Anyway, I believe I'm done with the Master Spartan 6 constraints file. The Xilinx ISE tool needs to identify clock inputs which is especially important, and then the names you choose to give the rest of the I/O pins. I've not named most of the address pins and all the data pins that go to the top 2 SyncRAMs. The reason is that I'm sorta of curious for an early experiment, if it actually matters, for resource usage or top speed, which I seriously doubt. I've found the Xilinx tools fully capable in something like this, but you never know. Maybe someone can chime in on this?

Tomorrow, onto the Slave Spartan 6 constraints file. I personally use the constraints file, which is necessary for ISE to compile the project, to double check the pin connections. I don't use schematics for large pin IC's, it's a waste of time IMO... Anyway, cheers!

Code:

# MASTER CLOCK IN #

# Main Clock #
NET "MAINCLK1" LOC = P55 | IOSTANDARD = LVCMOS33;  //N_GCLK
NET "MAINCLK1" TNM_NET = "MAINCLK1";
TIMESPEC TS_MAINCLK1 = PERIOD "MAINCLK1" 6.734 ns HIGH 50 %; //148.5MHz

# MASTER CLOCKS OUT and SERIAL I/O #

# Digital Audio Clock #
NET "DACLK" LOC = P50 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //N_GCLK, U21 Pin 39. 24.576MHz

# SPI (U10) & USB (U11) Clock #
NET "USBSPICLK" LOC = P132 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //P_GCLK, U10 Pin 11, U11 Pin 19. 12MHz

# Pixel Clock Out #
NET "PCLKOUT" LOC = P123 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //N_GCLK, U2 Pin 51. 148.5MHz

# FPGA Master (U3) to USB (U11)
NET "USBRx" LOC = P111 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //USER I/O, U11 Pin 9
NET "USBTx" LOC = P112 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //USER I/O, U11 Pin 7

# SPI Flash Clock & Data #
NET "SCLK" LOC = P132 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //P_GCLK, U10 Pin 14, U8 Pin 6 
NET "SO" LOC = P120 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //VREF, U10 Pin 16
NET "SI" LOC = P121 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //USER I/O, U10 Pin 15
NET "SD/FLASHn" LOC = P137 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //USER I/O, U10 Pin13, U9 Pin 2

# I2C #
NET "SDA" LOC = P47 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //RDRW_B_VREF
NET "SCL" LOC = P133 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //N_GCLK

# Master FPGA (U3) Synchronous Rams Signals #
NET "SRAddr[]" LOC = P9 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //USER I/O, U5 Pin 50
NET "SRAddr[]" LOC = P10 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //USER I/O, U5 Pin 49
NET "SRAddr[]" LOC = P11 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //USER I/O, U5 Pin 48
NET "SRAddr[]" LOC = P12 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //USER I/O, U5 Pin 47
NET "SRAddr[]" LOC = P14 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //N_GCLK, U5 Pin 46
NET "SRAddr[]" LOC = P15 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //P_GCLK, U5 Pin 45
NET "SRAddr[]" LOC = P16 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //N_GCLK, U5 Pin 44
NET "SRAddr[]" LOC = P17 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //P_GCLK, U5 Pin 43
NET "SRAddr[A0]" LOC = P21 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //N_GCLK, U5 Pin 37
NET "SRAddr[A1]" LOC = P22 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //P_GCLK, U5 Pin 36
NET "SRAddr[]" LOC = P23 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //N_GCLK, U5 Pin 35
NET "SRAddr[]" LOC = P24 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //P_GCLK, U5 Pin 34
NET "SRAddr[]" LOC = P26 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //USER I/O, U5 Pin 33 
NET "SRAddr[]" LOC = P27 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //USER I/O, U5 Pin 32
NET "SRAddr[]" LOC = P45 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //D0-D15, U5 Pin 99
NET "SRAddr[]" LOC = P46 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //D0-D15, U5 Pin 100
NET "SRAddr[]" LOC = P51 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //P_GCLK, U5 Pin 42
NET "SRAddr[]" LOC = P127 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //P_GCLK, U5 Pin 82
NET "SRAddr[]" LOC = P138 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //USER I/O, U5 Pin 81
NET "SRAddr[]" LOC = P139 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //USER I/O, U5 Pin 83
NET "SRAddr[]" LOC = P140 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //USER I/O, U5 Pin 84
NET "SRAddr[]" LOC = P141 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //USER I/O, U5 Pin 80
NET "SRAddr[]" LOC = P44 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //D0-D15, U5 Pin 98

NET "SRD[]" LOC = P1 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //VREF, U5 Pin 69
NET "SRD[]" LOC = P2 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //USER I/O, U5 Pin 68
NET "SRD[]" LOC = P5 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //USER I/O, U5 Pin 63
NET "SRD[]" LOC = P6 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //USER I/O, U5 Pin 62
NET "SRD[]" LOC = P7 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //USER I/O, U5 Pin 59
NET "SRD[]" LOC = P8 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //USER I/O, U5 Pin 58
NET "SRD[]" LOC = P30 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //USER I/O, U5 Pin 23 
NET "SRD[]" LOC = P32 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //USER I/O, U5 Pin 22
NET "SRD[]" LOC = P33 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //USER I/O, U5 Pin 19
NET "SRD[]" LOC = P34 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //VREF, U5 Pin 18
NET "SRD[]" LOC = P35 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //USER I/O, U5 Pin 13
NET "SRD[]" LOC = P40 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //D0-D15, U5 Pin 12
NET "SRD[]" LOC = P41 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //D0-D15, U5 Pin 9
NET "SRD[]" LOC = P43 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //D0-D15, U5 Pin 8
NET "SRD[]" LOC = P142 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //USER I/O, U5 Pin 73
NET "SRD[]" LOC = P143 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //VREF, U5 Pin 72

NET "SRWEn" LOC = P29 |IOSTANDARD = LVCMOS33 |SLEW = FAST |DRIVE = 12;  //USER I/O, U5 Pin 88
NET "SRCLK" LOC = P134 |IOSTANDARD = LVCMOS33 |SLEW = FAST |DRIVE = 12;  //P_GCLK, U5 Pin 89

# FPGA Master (U3) to FPGA Slave (U2) Bi-Directional Comm #
NET "COMM0" LOC = P48 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //DO-D15, U2 Pin 120
NET "COMM1" LOC = P56 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //P_GCLK, U2 Pin 119
NET "COMM2" LOC = P57 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //D0-D15, U2 Pin 118
NET "COMM3" LOC= P58 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //D0-D15, U2 Pin 117
NET "COMM4" LOC = P59 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //D0-D15, U2 Pin 116
NET "COMM5" LOC = P61 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //D0-D15, U2 Pin 115
NET "COMM6" LOC = P62 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //D0-D15, U2 Pin 114
NET "COMM7" LOC = P66 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //USER I/O, U2 Pin 112
NET "COMM8" LOC = P67 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //USER I/O, U2 Pin 111
NET "COMM9" LOC = P74 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //DOUT_BUSY, U2 Pin 105
NET "COMM10" LOC = P75 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //AWAKE, U2 Pin 104
NET "COMM11" LOC = P78 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //USER I/O, U2 Pin 102
NET "COMM12" LOC = P79 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //USER I/O, U2 Pin 101
NET "COMM13" LOC = P80 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //USER I/O, U2 Pin 100
NET "COMM14" LOC = P81 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //USER I/O, U2 Pin 99
NET "COMM15" LOC = P82 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //USER I/O, U2 Pin 98
NET "COMM16" LOC = P83 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //USER I/O, U2 Pin 97
NET "COMM17" LOC = P84 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //N_GCLK, U2 Pin 95
NET "COMM18" LOC = P85 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //P_GCLK, U2 Pin 94
NET "COMM19" LOC = P87 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //N_GCLK, U2 Pin 93
NET "COMM20" LOC = P88 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //P_GCLK, U2 Pin 92
NET "COMM21" LOC = P93 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //P_GCLK, U2 Pin 87
NET "COMM22" LOC = P94 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //N_GCLK, U2 Pin 85
NET "COMM23" LOC = P95 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //P_GCLK, U2 Pin 84
NET "COMM24" LOC = P97 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //P_GCLK, U2 Pin 83
NET "COMM25" LOC = P98 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //USER I/O, U2 Pin 82
NET "COMM26" LOC = P99 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //USER I/O, U2 Pin 81
NET "COMM27" LOC = P100 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //USER I/O, U2 Pin 80
NET "COMM28" LOC = P101 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //USER I/O, U2 Pin 79
NET "COMM29" LOC = P102 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //USER I/O, U2 Pin 78
NET "COMM30" LOC = P104 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //VREF, U2 Pin 75
NET "COMM31" LOC = P105 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;  //USER I/O, U2 Pin 74

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502

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ElEctric_EyE

Post subject: Re: A/V SBC with Multiple 65xxx CPUs

Posted: Sun Feb 16, 2020 7:07 pm

Joined: Mon Mar 02, 2009 7:27 pm
Posts: 3258
Location: NC, USA

90% done with the Slave Spartan 6 constraints file. I did find one via on the bottom SyncRAM that should go to ground but was left open. Not a show stopper, but a version 1.8 continues with yet another correction. All that's left are some of the pins assigned to the videoDAC.

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502

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ElEctric_EyE

Post subject: Re: A/V SBC with Multiple 65xxx CPUs

Posted: Tue Feb 18, 2020 9:33 pm

Joined: Mon Mar 02, 2009 7:27 pm
Posts: 3258
Location: NC, USA

So now it's time to finally focus on the Verilog. I think the strategy I'm going to use is the program the Slave Spartan 6 first and have it output RGB data read from the SyncRAM to the videoDAC. I have a project file already completed that I'd used for the later stages of the PVB project. It uses a 65Org16.d core running @74Mhz, 1/2 the video speed. The .d core has a couple more features I added and had not updated the Github in my sig below. You can see the extra features in the notes above the cpu.v pic I took below. I really got deep and it will take time to re-familiarize myself with the Verilog but I don't foresee any problems. Let me just give credit to those who had helped me get to this stage: Arlet Ottens, BigEd & Michael Morris. I seriously would have not even started the PVB project if I thought I was not going to get help. After experimenting with Arlet's core for a couple years, I learned how to do state machines which perform different functions, cycle by cycle. Very powerful stuff and sorta difficult to wrap my brain around it all the first time around. This time should be even better I'm hoping!

Another thing I realized is my block diagram is incorrect, I'll have to make a new one. The Master Spartan 6 controls ALL the I/O. I think at one point I had tried to fit the USB controller Tx & Rx into the bottom S6 but there were no pins left. I was hoping to at least have keyboard input for some sort of control without having both FPGAs... I won't be able to reprogram the Si514 which isn't a big deal. I'll just have to use the 40MHz coming from it and have the Slave S6 do its magic and generate the 148.5 MHz pixel clock. The Si514 I2C programming will be done by the Master S6 when the time comes. I'll attempt to make a state machine for that as well.

In the 1st pic, you can see the project file, which I'll go into in the following post. You can see the PLL, which is a very powerful feature of the S6. I believe it has 2 of these for the 144-pin version I'm using, IIRC.
The 2nd pic shows credits and features of the 65Org16.d core. 16 16-bit Accumulators, 2 index registers Y & W and based off the 6502 and able to run @least 74MHz with this project 'in tow'. Yummy

Attachments:

Slave.Project.File.jpg [ 754.09 KiB | Viewed 1372 times ]

65Org16.d.core.jpg [ 994.91 KiB | Viewed 1372 times ]

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

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ElEctric_EyE

Post subject: Re: A/V SBC with Multiple 65xxx CPUs

Posted: Tue Feb 18, 2020 10:16 pm

Joined: Mon Mar 02, 2009 7:27 pm
Posts: 3258
Location: NC, USA

In this project, going top to bottom on the left hand, I had:
1) A PLL generate 3 separate 148.5 MHz signals for off FPGA use and the internal 65Org16 74.25MHz signal.
2) SRCLKOUT, PCLKOUT & VCLKOUT were the buffered 148.5MHz going to the SyncRAM, videoDAC and the next PVB pixelCLK.
3) cpu.v & ALU.v is the 65Org16.d
4) AddrDECODE is for the FPGA internal block RAM used for Zero Page and the STack.
5,6) ZPRAM & STRAM are 1Kx16 each for internal FPGA block RAM.
7,8) SCRATCHRAMX & SCRATCHRAMY. 16Kx16 ea for reference points for video plotting.
9) SYSROM is 4Kx16 of FPGA internal block RAM used for the operating SYStem.
10) HVSync is a highly modified video generator originally made by Arlet.
11,12) sincos2 & sincos are generated by Xilinx tools and the waveforms are stored in the SCRATCHRAMX & SCRATCHRAMY for on the fly reference points for plotting.
13) CharROM was a 1Kx16 FPGA internal block RAM for IBM and C-64 character data.
14) PRBS_ANY is a pseudo-random number generator.
15) RESET is an outside signal that is delayed internally by 64 cycles.
16) ROM is the OS. 4Kx16
17) constraint.ucf is similar to what I've been working on for the past couple days.

I can't believe it's been 6 years!!!

What I don't see are the line and circle hardware plotters. Will search for them.

Attachments:

2014.Paralle.Video.Board.Project.jpg [ 547.12 KiB | Viewed 1369 times ]

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502

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ElEctric_EyE

Post subject: Re: A/V SBC with Multiple 65xxx CPUs

Posted: Tue Feb 18, 2020 10:47 pm

Joined: Mon Mar 02, 2009 7:27 pm
Posts: 3258
Location: NC, USA

Here are some videos I made, I intend to make many more.
Hardware Bresenham line drawing
Hardware Circles and lines
Vector graphics using the sin/cos in the FPGA SCRATCHRAMs and drawing lines to the XY coordinates @1080p. Watch how much faster! I think it was plotting during HSYNC & VSYNC retrace too. This is nothing to what's coming up in this current project!

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502

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ElEctric_EyE

Post subject: Re: A/V SBC with Multiple 65xxx CPUs

Posted: Wed Feb 19, 2020 9:47 pm

Joined: Mon Mar 02, 2009 7:27 pm
Posts: 3258
Location: NC, USA

The last couple posts I intended to give examples only, the real project file(s) for the Slave & Master will start out much, much simpler. Today I finished the Slave S6 constraints file and most of the Master S6. I say most of the Master S6 constraints because there are about 10 pins that are connected to free/unused vias that are meant for ICs which are not soldered to the board yet.
As mentioned before, ALL the Slave S6 pins are used for FPGA-FPGA Communications, RGB-out from Master to RGB-in to Slave and SyncRAM address/data/control pins.
To finish off today, I'll start trimming the project file for the Slave S6 and adjust the settings for the PLL clock generator for generating 148.5Mhz from 40MHz.

Attachments:

Master&Slave.ucf.file.jpg [ 3.41 MiB | Viewed 1335 times ]

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ElEctric_EyE

Post subject: Re: A/V SBC with Multiple 65xxx CPUs

Posted: Thu Feb 20, 2020 9:45 pm

Joined: Mon Mar 02, 2009 7:27 pm
Posts: 3258
Location: NC, USA

I forgot to give credit to Bitwise! His Java creation, As65 made it so I could add new opcodes and make a program for the 65Org16 compile! I hope it still works on Windows 10. Will see soon, first to get the hardware working again. Oh no, his site is down.
I finally found a project file that has all the info needed. It has the ISE project file and all the files needed on the software end too. It's a later version where it successfully merged incoming RGB data to another boards RGB data.
I decided it's actually best to keep the project intact, as it is proven although on another albeit similar board. Now on to putting the new constraints (.ucf) file into the old project...

Attachments:

As65.jpg [ 339.33 KiB | Viewed 1307 times ]

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

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GARTHWILSON

Post subject: Re: A/V SBC with Multiple 65xxx CPUs

Posted: Thu Feb 20, 2020 10:17 pm

Joined: Fri Aug 30, 2002 1:09 am
Posts: 8543
Location: Southern California

ElEctric_EyE wrote:

I forgot to give credit to Bitwise! [...] Oh no, his site is down.

I knew I had a link to his As65 assembler on my links page, so I just tried it, and it came right up. Are you using http://www.obelisk.me.uk/ ?

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

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ElEctric_EyE

Post subject: Re: A/V SBC with Multiple 65xxx CPUs

Posted: Fri Feb 21, 2020 7:55 pm

Joined: Mon Mar 02, 2009 7:27 pm
Posts: 3258
Location: NC, USA

GARTHWILSON wrote:

ElEctric_EyE wrote:

I forgot to give credit to Bitwise! [...] Oh no, his site is down.

I knew I had a link to his As65 assembler on my links page, so I just tried it, and it came right up. Are you using http://www.obelisk.me.uk/ ?

No, I tried the old site. Thanks Garth, I got it!

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502

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ElEctric_EyE

Post subject: Re: A/V SBC with Multiple 65xxx CPUs

Posted: Sat Feb 22, 2020 9:57 pm

Joined: Mon Mar 02, 2009 7:27 pm
Posts: 3258
Location: NC, USA

Bad news and... more bad news.
As65 will not run on Win10. This weekend I'm re-purposing an older desktop computer for windows XP SP2 and moving the project to that computer.
I've finally fit the new board's .ucf file into the old project above and nothing happens. The scope shows the 40MHz clock oscillator looking pretty clean, but no clock signals out of the Slave Spartan 6. Looking over the messages from ISE, nothing is indicating the tools have deleted any of the modules so I'm suspecting bad solder joints. I don't suspect the FPGA FLASH PROM as iMPACT can perform all functions on the FPGA itself or the FLASH PROM. I'm happy with that fact.

So now this is getting serious and I'm going to clean up the clutter and dedicate a desk to this project! Desktop computer, oscilloscope, microscope, soldering iron, hot plate. Straight down into that bare metal! :lol:

When I get to the old folks home, this is all I'm going to need.

BTW, any Doctor Who fans here? I'm selling books on eBay under alias ultimateroadwarrior9.

Attachments:

Future.Project.Desk.jpg [ 479.32 KiB | Viewed 1245 times ]

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

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BitWise

Post subject: Re: A/V SBC with Multiple 65xxx CPUs

Posted: Sat Feb 22, 2020 10:35 pm

Joined: Tue Mar 02, 2004 8:55 am
Posts: 996
Location: Berkshire, UK

My As65 runs under Windows 10 but you have to install a Java runtime.

_________________
Andrew Jacobs
6502 & PIC Stuff - http://www.obelisk.me.uk/
Cross-Platform 6502/65C02/65816 Macro Assembler - http://www.obelisk.me.uk/dev65/
Open Source Projects - https://github.com/andrew-jacobs

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BigDumbDinosaur

Post subject: Re: A/V SBC with Multiple 65xxx CPUs

Posted: Sun Feb 23, 2020 6:54 am

Joined: Thu May 28, 2009 9:46 pm
Posts: 8504
Location: Midwestern USA

ElEctric_EyE wrote:

Bad news and... more bad news.
As65 will not run on Win10. This weekend I'm re-purposing an older desktop computer for windows XP SP2 and moving the project to that computer.

If you can get your hands on it, XP SP3 is better.

_________________
x86? We ain't got no x86. We don't NEED no stinking x86!

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ElEctric_EyE

Post subject: Re: A/V SBC with Multiple 65xxx CPUs

Posted: Sun Feb 23, 2020 5:21 pm

Joined: Mon Mar 02, 2009 7:27 pm
Posts: 3258
Location: NC, USA

BitWise wrote:

My As65 runs under Windows 10 but you have to install a Java runtime.

I installed the 64-bit version, down below, since I use Win10 x64. It's been awhile since I used your program, I've forgotten alot. But when I double click on As65.exe it gives me 'This app can't run on your PC' message. Thanks for your help again!

Attachments:

JRE.jpg [ 340.24 KiB | Viewed 1205 times ]

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

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BitWise

Post subject: Re: A/V SBC with Multiple 65xxx CPUs

Posted: Sun Feb 23, 2020 5:43 pm

Joined: Tue Mar 02, 2004 8:55 am
Posts: 996
Location: Berkshire, UK

HHmm, I don't distribute the code as .EXE file. It comes as a .JAR and you invoke it via the java command in a shell, batch or makefile.

Code:

        java -classpath Dev65.jar uk.co.demon.obelisk.w65xx.As65 boot.asm
Warning: ascii.inc (30) This label is a reserved word (STX)
        java -classpath Dev65.jar uk.co.demon.obelisk.w65xx.Lk65 -code "$008000-$00ffff" -bin -output boot.rom boot.obj
        java -classpath Dev65.jar uk.co.demon.obelisk.w65xx.As65 basic.asm
Warning: ascii.inc (30) This label is a reserved word (STX)
        java -classpath Dev65.jar uk.co.demon.obelisk.w65xx.Lk65 -code "$c00000-$c01fff" -bss "$c10000-$c1ffff" -s28 -output basic.s28 basic.obj

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