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Ohhhh, the rtf65002. 32-bit databus, 34 bit address bus? Nice.
Yes, 34 bits address. Data is a flat 32 bits so the 2 LSB of a (byte) data address are always zero.
Address specs for data specify a 32 bit word address not a byte address hence two extra address bits.
Addressing is 16GB (4GW) for data, 4GB for code. (Code is byte addressed).
rtf65002
- 65C02 like instruction set + RISC like instructions
- instruction vary from 1 to 7 bytes
- 16 32 bit registers plus stack pointer, r1 = acc, r2 = x, r3 = y
- zero page memory is 4kW in size
- entire instructions are fetched from the cache
* non cached instruction execution is horrendously slow, the cpu has to fetch 3 words from memory for each instruction because it doesn't know how big the instruction is until the DECODE state, but fetching takes place in the IFETCH state. So the cpu assumes the worst, a 7 byte poorly aligned instruction. I'm assuming one would want to use the I-Cache most of the time.