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 Post subject: Re: Cache in FPGA
PostPosted: Wed Aug 28, 2013 6:49 am 
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Working on the rtf65002.....
I've tightly coupled the cache to the processer, so cache considerations show up in state machine states.
I'm using write-through with no write allocate.
The following Verilog code shows how the cache impacts things.

wadr = cache write address
radr = cache read address
wdat = data to write to cache
rdat = data read from cache
Code:
// Stores always write through to memory, then optionally update the cache if
// there was a write hit.
STORE1:
   begin
      cyc_o <= 1'b1;
      stb_o <= 1'b1;
      we_o <= 1'b1;                   
      sel_o <= 4'hf;                     // select all byte lanes
      adr_o <= {wadr,2'b00};
      dat_o <= wdat;
      radr <= wadr;      // Do a cache read to test the hit
      state <= STORE2;
   end
   
// Terminal state for stores. Update the data cache if there was a cache hit.
// Clear any previously set lock status
STORE2:
   if (ack_i) begin
      lock_o <= 1'b0;
      cyc_o <= 1'b0;
      stb_o <= 1'b0;
      we_o <= 1'b0;
      sel_o <= 4'h0;
      adr_o <= 34'h0;
      dat_o <= 32'h0;
      if (dhit) begin                // we would set dmiss = `TRUE in the else for a write-allocate cache
         wr <= 1'b1;
      end
      state <= IFETCH;
   end


// Handle the following address modes: zp : zp,Rn : abs : abs,Rn
LOAD1:
   if (unCachedData) begin
      if (isRMW)
         lock_o <= 1'b1;
      cyc_o <= 1'b1;
      stb_o <= 1'b1;
      sel_o <= 4'hf;
      adr_o <= {radr,2'b00};
      state <= LOAD2;
   end
   else if (dhit) begin
      b <= rdat;
      state <= CALC;
   end
   else
      dmiss <= `TRUE;
LOAD2:
   if (ack_i) begin
      cyc_o <= 1'b0;
      stb_o <= 1'b0;
      sel_o <= 4'h0;
      b <= dat_i;
      state <= CALC;
   end

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 Post subject: Re: Cache in FPGA
PostPosted: Wed Aug 28, 2013 1:59 pm 
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Location: NC, USA
Ohhhh, the rtf65002. 32-bit databus, 34 bit address bus? Nice.

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 Post subject: Re: Cache in FPGA
PostPosted: Wed Aug 28, 2013 7:22 pm 
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Joined: Sun Dec 29, 2002 8:56 pm
Posts: 460
Location: Canada
Quote:
Ohhhh, the rtf65002. 32-bit databus, 34 bit address bus? Nice.


Yes, 34 bits address. Data is a flat 32 bits so the 2 LSB of a (byte) data address are always zero.
Address specs for data specify a 32 bit word address not a byte address hence two extra address bits.
Addressing is 16GB (4GW) for data, 4GB for code. (Code is byte addressed).

rtf65002
- 65C02 like instruction set + RISC like instructions
- instruction vary from 1 to 7 bytes
- 16 32 bit registers plus stack pointer, r1 = acc, r2 = x, r3 = y
- zero page memory is 4kW in size
- entire instructions are fetched from the cache

* non cached instruction execution is horrendously slow, the cpu has to fetch 3 words from memory for each instruction because it doesn't know how big the instruction is until the DECODE state, but fetching takes place in the IFETCH state. So the cpu assumes the worst, a 7 byte poorly aligned instruction. I'm assuming one would want to use the I-Cache most of the time.

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 Post subject: Re: Cache in FPGA
PostPosted: Sat Sep 28, 2013 3:23 pm 
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Joined: Sun Dec 29, 2002 8:56 pm
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Location: Canada
[url]rtf6502/trunk/rtl/verilog/cache6502.v[/url]

I've created a core for a 6502 cache. It's on github.
It's organized with a cpu side and a memory side. The cpu side is a typical 6502 interface, the memory side is a 32 bit wide WISHBONE burst interface. There's a simple testbench included and it looks like it'd work.

It needs to be tested.

This is my first boo at github.

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 Post subject: Re: Cache in FPGA
PostPosted: Sat Sep 28, 2013 4:01 pm 
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Joined: Thu Dec 11, 2008 1:28 pm
Posts: 10977
Location: England
Thanks Rob! (Link not quite right: https://github.com/robfinch/Cores/blob/ ... ache6502.v works)


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