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PostPosted: Wed Nov 27, 2013 5:25 am 
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Here is the 1K x 16 BRAM module:
Code:
module BRAM1KX16 (
  input CLK
, input [9:0] A
, output [15:0] DO
, input  [15:0] DI
, input EN
, input WR
);
(*LOC="RAMB16_X0Y0"*)
RAMB16_S18
#(  .INIT(18'h00000),.SRVAL(18'h00000))
bram0(
  .CLK(CLK), .ADDR(A[9:0]), .DO(DO[15:0]), .DI(DI[15:0]),  .WE(WR&EN),
  .EN(1), .SSR(~EN), //on deselect, output 00
  .DIP(0)
);
endmodule


Note that the LOC directive matches the .bmm file's x-y coordinates. Also, I instantiate this module as 'bram', therefore the name in the .bmm file is 'bram/bram0'

On the topic of .bmm naming conventions - I assumed that the picoblaze name is just a symbol and does not affect anything.

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PostPosted: Wed Nov 27, 2013 3:53 pm 
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Joined: Mon Apr 23, 2012 12:28 am
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Location: Huntsville, AL
Yes, the name given in the BMM file for the block RAM is just a name. Any relation to the Xilinx soft-core processors is just a coincidence. It appears that Data2MEM does not place any restrictions on the reference provided for the block RAM array specified in the BMM file.

The examples given in the Data2MEM user's guide do give the impression that the tool was designed specifically to patch program and data memory for Xilinx soft-core processors. It is a good thing that is not the case, and that it can be used for the purpose of patching the block RAM initialization data of any configuration bit stream.

Your module is instantiating an HDL library element for the Spartan-3 family. In regards to your question of how to use Data2MEM with multiple block RAMs, I will try the following:

Code:
module BRAM4KX16 (
  input  CLK
, input  [11:0] A
, output [15:0] DO
, input  [15:0] DI
, input  EN
, input  WR
);

//  MAM, 13K27, Increase memory array from 1024 x 16 to 4096 x 16.

assign RAM_EN0 = EN & (A[11:10] == 2'b00);

(*LOC="RAMB16_X0Y0"*)
RAMB16_S18
#(  .INIT(18'h00000),.SRVAL(18'h00000))
bram0(
  .CLK(CLK), .ADDR(A[9:0]), .DO(DO[15:0]), .DI(DI[15:0]),  .WE(WR&RAM_EN0),
  .EN(1), .SSR(~RAM_EN0), //on deselect, output 00
  .DIP(0)
);

assign RAM_EN1 = EN & (A[11:10] == 2'b01);

(*LOC="RAMB16_X0Y1"*)
RAMB16_S18
#(  .INIT(18'h00000),.SRVAL(18'h00000))
bram1(
  .CLK(CLK), .ADDR(A[9:0]), .DO(DO[15:0]), .DI(DI[15:0]),  .WE(WR&RAM_EN1),
  .EN(1), .SSR(~RAM_EN1), //on deselect, output 00
  .DIP(0)
);

assign RAM_EN2 = EN & (A[11:10] == 2'b10);

(*LOC="RAMB16_X0Y3"*)
RAMB16_S18
#(  .INIT(18'h00000),.SRVAL(18'h00000))
bram2(
  .CLK(CLK), .ADDR(A[9:0]), .DO(DO[15:0]), .DI(DI[15:0]),  .WE(WR&RAM_EN2),
  .EN(1), .SSR(~RAM_EN2), //on deselect, output 00
  .DIP(0)
);

assign RAM_EN3 = EN & (A[11:10] == 2'b11);

(*LOC="RAMB16_X0Y3"*)
RAMB16_S18
#(  .INIT(18'h00000),.SRVAL(18'h00000))
bram3(
  .CLK(CLK), .ADDR(A[9:0]), .DO(DO[15:0]), .DI(DI[15:0]),  .WE(WR&RAM_EN3),
  .EN(1), .SSR(~RAM_EN3), //on deselect, output 00
  .DIP(0)
);

endmodule


Code:
ADDRESS_SPACE bram RAMB16 INDEX_ADDRESSING [0x00000000:0x00001FFF]
 
  // Address Range: 0x0000:0x07FF -- Each Block RAM is 2kB in size.

  BUS_BLOCK
    bram/bram0 [15:0] PLACED = X0Y0;
  END_BUS_BLOCK;
 
  // Address Range: 0x0800:0x0FFF -- Each Block RAM is 2kB in size.
 
  BUS_BLOCK
    bram/bram1 [15:0] PLACED = X0Y1;
  END_BUS_BLOCK;
 
  // Address Range: 0x1000:0x17FF -- Each Block RAM is 2kB in size.
 
  BUS_BLOCK
    bram/bram2 [15:0] PLACED = X0Y2;
  END_BUS_BLOCK;
 
  // Address Range: 0x1800:0x1FFF -- Each Block RAM is 2kB in size.
 
  BUS_BLOCK
    bram/bram3 [15:0] PLACED = X0Y3;
  END_BUS_BLOCK;

END_ADDRESS_SPACE;


You may have already tried something like this. If so, let me know. I've got a couple of other ideas to try.

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PostPosted: Wed Nov 27, 2013 5:48 pm 
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In this situation, it would make more sense to wire the BRAMs as 4 4-bit BRAMS, each responsible for 4 bits out of 16. This way they can all share the address lines, avoiding address decoding logic as well as the 4-1 mux at the end. The .bmm file is then (I think)
Code:
ADDRESS_SPACE bram RAMB16 INDEX_ADDRESSING [0x00000000:0x00001FFF]
  BUS_BLOCK
    bram/bram0 [3:0] PLACED = X0Y0;
    bram/bram1 [7:4] PLACED = X0Y1;
    bram/bram2 [11:8] PLACED = X0Y2;
    bram/bram3 [15:12] PLACED = X0Y3;
  END_BUS_BLOCK;
END_ADDRESS_SPACE;


The instantiation code is trivial, just wire up the right bits to the right BRAM data bus.

Confusing points: Which bits go where? I never got this to work, but mostly because I was still debugging the 65Org16 circuit and nothing really worked. There are a few opportunities to place the bits backwards, wire the BRAMS backwards, etc.

In my case I am happy with just a single BRAM (1K) bootloader, so it's an academic point.

Michael, your instantiation code above has a typo - the LOC directive for "RAMB16_X0Y3" is repeated twice and X0Y2 is never used...

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PostPosted: Wed Nov 27, 2013 8:29 pm 
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Joined: Mon Apr 23, 2012 12:28 am
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Thanks, typo from copying and pasting blocks of code.

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