I have a Sipeed Tang Nano 9K on my desk in-front of me and insufficient time this week to start to use it. It can drive HDMI and a local LCD display. It's not for a 65xx project but there will be space left-over for a 6502 and maybe a 65816, so who knows.

-Gordon

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Gordon Henderson.
See my Ruby 6502 and 65816 SBC projects here: https://projects.drogon.net/ruby/

So I got my VGAController playing along nicely with the CPU timeslices but I'm still not happy - namely that I ended up in a bit of mess wondering how I could stream the VGA primary buffer but at the "same time" make modifications to a secondary framebuffer.

I found that I could actually push my RAM controller up to 50MHz so I'm going to implement something similar to the odd/even cycle idea. My RAM controller needs 2 cycles to perform a RAM read so I'm going to change it to alternate between VGA reads, Blitter function and the 6502 CPU timeslice.. but not today.

The "Blitter" in my case will be some logic in the FPGA to render the screen text into a secondary buffer while the VGA is being displayed from the primary buffer. Once the Blitter has rendered everything it will swap the primary and secondary address pointers so the secondary becomes the primary and vice versa.

Unfortunately.. this isn't going to happen today.

Historical 6502 systems had very fine grain time-slicing but if you're using SDRAM or similar (with two or more clock cycle access latency) then accessing in large bursts is the most sensible option by far.

If the display is write only (or blitter only), all writes (or blitter commands) can be written to FIFO and the granularity of the video time-slicing is immaterial. Likewise, the speed of the processor and display are mostly unimportant.



You have considerable restraint. I would have increased the resolution by a factor of four. Or added a second display output. Or gone mad with sprites. Or added a co-processor. Or a networking interface. Or sound.



Oh! That's why, in the Commodore 64, the VIC-II pauses the processor three cycles ahead! Unfortunately, this may be one bad design decision influencing another. I suspect that the legacy RDY for read only was due to the processor designers only considering wait states for cheap, slow ROM and not the general case. I've done similar with a board design, so I can appreciate the error.

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Modules | Processors | Boards | Boxes | Beep, Beep! I'm a sheep!