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Using CPLD for very fine-grained memory mapping... http://forum.6502.org/viewtopic.php?f=10&t=5753 |
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Author: | BitWise [ Fri Sep 20, 2019 7:30 am ] |
Post subject: | Re: Using CPLD for very fine-grained memory mapping... |
barrym95838 wrote: Another would be to steal $0000 -> $007f for I/O, allowing for faster and shorter access. Of course, you're left with only 128 bytes of ZP RAM, but that ought to be enough for anybody!! The Rockwell microcontrollers (6501/6541) and WDC's 65C134 map hardware into zero page. It makes the SMB, RMB, BBR and BBS instructions which only support zero page addresses extremely useful for examining and tweaking I/O registers. Rockwell also relocated the stack to page zero so one continous on chip RAM area serves for stack and user variables. The 65C134 can map its stack to $40-$FF if you clear some control bits. |
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