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| Optimizing 6502 core performance in FPGA environments http://forum.6502.org/viewtopic.php?f=10&t=4559 |
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| Author: | BigEd [ Sun May 28, 2017 6:15 am ] |
| Post subject: | Re: Optimizing 6502 core performance in FPGA environments |
It's true, I've only looked at devices on moderately affordable dev boards, and favouring Xilinx. I haven't checked the numbers, but it's possible that Altera have made the tactical choice to dedicate a bit more of the die to on-chip RAM - it's dense by nature, so a small difference in ratio could be a large increase in capacity. |
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| Author: | Windfall [ Sun May 28, 2017 10:04 am ] |
| Post subject: | Re: Optimizing 6502 core performance in FPGA environments |
Altera and Xilinx are definitely the big players. Their small chips are sold by fat Joes with cigars at fairs, their big ones probably come with a free hardware engineer if you buy enough. The fallout to development boards is probably no different either. |
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| Author: | BigEd [ Sun May 28, 2017 10:33 am ] |
| Post subject: | Re: Optimizing 6502 core performance in FPGA environments |
Interesting idea to write a design in microcoded style, for simplicity and maintainability, and then implement the microcode in logic. We usually have lots of logic capacity. Indeed, using distributed RAM should be efficient and hopefully also fast, although the speed of the result does remain to be seen. |
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| Author: | Windfall [ Sun May 28, 2017 11:26 am ] |
| Post subject: | Re: Optimizing 6502 core performance in FPGA environments |
BigEd wrote: Interesting idea to write a design in microcoded style, for simplicity and maintainability, and then implement the microcode in logic. We usually have lots of logic capacity. Indeed, using distributed RAM should be efficient and hopefully also fast, although the speed of the result does remain to be seen. You may be surprised to see how ROM is implemented in logic. It actually works out very well. A ROM is basically just a collection of 'if <address x> then <data y>'. Which is exactly what the original form of programmable logic (basically an OR of ANDs) does really well, and consequently needs very few cells for. The contemporary form (LUTs) : exactly the same thing (but even more flexible). I'd highly recommend having a (regular) look at netlists. Under Quartus, these are at Tools -> Netlist Viewers. This gives you a very good idea of what is being baked by the compiler, given your verilog or VHDL ingredients. Very enlightening. As is : knowing the underlying structure of your cells. |
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