John West wrote:
The ATF1504AS has 64 macrocells, each with 5 product terms. Since you've got the 44 pin version, there are many macrocells not connected to pins. If you need more than 5 product terms anywhere, you can put some into one of the unconnected macrocells and feed its output back into the matrix. But that adds to the delay.
Logic doubling in the ATF150x series, which is the process of "borrowing" otherwise unused macrocells (MCs) to implement complicated logic that would otherwise fail with a "too many product terms" error, is a very useful feature that does not significantly affect pin-to-pin propagation time. Use of pin nodes (discussed below) and cascaded logic add a small amount of internal prop time that can be largely ignored in 65C02 or 65C816 designs, even at 20 MHz. So don't hesitate to use these capabilities in your designs.
One can specify logic doubling in the CUPL source file, and the "borrowing" of unused MCs will occur automatically as needed. The statement is as follows:
Code:
property atmel {logic_doubling=on};
Property statements must be placed in the file after the device declaration but before any pin assignments or logic statements. Here are the property statements I used in the CUPL code for POC V2's CPLD design:
Code:
property atmel {cascade_logic=on};
property atmel {logic_doubling=on};
property atmel {output_fast=off};
property atmel {pin_keep=off};
property atmel {preassign=keep};
property atmel {security=off};
property atmel {xor_synthesis=on};
The
property atmel {output_fast=off}; statement is interesting. This statement sets the output slew rate to fast or slow, and could be useful in diagnosing circuit instability problems. Even when set to slow, as is the above case, slew is still quite fast. I plan to try it both ways once I get POC V2 constructed.
Also useful are "pin nodes," which can be described as "virtual" pins. Pin nodes are the key to setting up latches and flops, as well as implementing state machines. Unlike using actual pins in a GAL, pin nodes don't use any physical resources and have a vanishingly small effect on total device propagation time.
Here are the pin node assignments I used for my POC V2 design:
Code:
/*
=========================
BURIED LOGIC DECLARATIONS
=========================
*/
pinnode = [blatch0..3]; /* bank address latches */
pinnode = [hmumcfg0..3]; /* hardware management unit */
pinnode = wsff; /* wait-state flip-flop */
pinnode = bank0; /* 1 = address is $000000-$00FFFF */
pinnode = basram; /* 1 = address is $000000-$00BFFF */
pinnode = bbus; /* 1 = valid bank address */
pinnode = cblk; /* 1 = address is $00C000-$00CFFF */
pinnode = dblk; /* 1 = address is $00D000-$00DFFF */
pinnode = eblk; /* 1 = address is $00E000-$00FFFF */
pinnode = extram; /* 1 = address is $010000-$07FFFF */
pinnode = hmusel; /* 1 = HMU being accessed */
pinnode = ioblk; /* 1 = I/O address space being accessed */
pinnode = iosel; /* 1 = I/O device selected */
pinnode = mcfgsel; /* 1 = HMU configuration being accessed */
pinnode = ramsel; /* 1 = RAM selected */
pinnode = rdflag; /* 1 = data fetch in progress */
pinnode = rdyout; /* 1 = MPU wait-stated */
pinnode = rhflag; /* 1 = data fetch on high clock */
pinnode = romsel; /* 1 = ROM selected */
pinnode = vab; /* 1 = address bus valid */
pinnode = vplatch; /* 1 = hardware vector being accessed */
pinnode = wdflag; /* 1 = data store in progress */
pinnode = wsflag; /* 1 = wait-state in progress */
The first, second and third pin node declarations set up D-type flip-flops and the rest act as flags.
One of the things I did when I developed my design was to allow the fitter to automatically assign pins for all signals that did not have to be attached to a specific pin. The JTAG pins, of course, are not assigned, since using them for logic I/O makes it impossible to subsequently reprogram the device via JTAG. I statically assigned the Ø2 input, as well as reset (RESB). Everything else was worked out by the fitter. The result was this:
Code:
R P
V V E V H G A A
D R W C P S D I N 1 1
1 D D C A B A 2 D 3 1
____________________________________
/ 6 5 4 3 2 1 44 43 42 41 40 \
TDI | 7 39 | A10
D2 | 8 38 | TDO
D0 | 9 37 | A9
GND | 10 36 | A8
IO0 | 11 35 | VCC
IO1 | 12 ATF1504 34 | A12
TMS | 13 44-Lead PLCC 33 | D3
RDY | 14 32 | TCK
VCC | 15 31 | RST
IO2 | 16 30 | GND
IO3 | 17 29 | ROM
| 18 19 20 21 22 23 24 25 26 27 28 |
\____________________________________/
I A A A G V R A A R R
O 1 1 1 N C W 1 1 A A
4 8 6 7 D C B 5 4 M M
1 0
From that, I did the PCB layout.
For the most part, one need not get overly concerned about how the internal "connections" are made. The purpose of having a programming language like CUPL is to relieve the designer of having to deal with the
tedious minutia of the CPLD's architecture. Back in the early days of programmable logic, the designer did have to deal with that stuff to stay within the limitations of the targeted device. Not so much anymore.
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