So I am ordering some parts tonight for this next project using the 65Org16.b core. I cannot call it a devboard anymore because I am planning multiple boards. Also, I am back to EPCB's miniboard pro service where one gets 3x 3.8"x2.5" 4 layer boards limited to 350 holes.

In V1.1, the spartan-6 was the centerpiece. Everything else was designed around it. In v1.2, the interface connector is the center of my concentration. It will be a female 96-pin DIN connector for data only, no power. The 3-row, right-angle, thru-hole connector is 3.7" long including mounting bolts so this is perfect for the edge of a miniboard pro board, although 96 holes of 350 max are gone right off the bat! Hence my new approach is to have several boards designed, each with their own 100MHz 65Org16.b core. More details later on inter-communications...

Right now I am planning for a video board with a DB15 VGA connector with 32MB of SDRam, and 256MBx16 30ns parallel FLASH, and a SDcard connector for icon/sprite video storage. Also, 2 FPGA FLASH Proms for 2 config's.

Another board strictly for audio. More boards can be added for more "voices". I started a thread somewhere here on 6502.org about a Digital Sound Synthesis board. It will follow this basic idea. More Flash/ SDcard connector. 2 more FLASH Proms for 2 config's.

Another board for all comm. This includes keyboard, mouse, USB to UART, some clock generation, wireless transmitters/receivers to future boards, and TFT output. If there has to be a master, this board would be it. 1 FPGA FLASH Prom here. It can also control which config Prom each dual config FPGA sees on reset.

The basic idea will be that each CPU can see into each other's 4GB memory space, none will overlap. Also each board will be able to receive commands, like higher level macro's. Like the video board will receive a macro command, let's say from the comm board, to plot a character or maybe change resolution or character size... The DSS board can bypass the video "macro" and directly access the video ram in order to plot a sampled waveform from it's memory.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Just a thought: do you have the room and the pins for two 16-bit wide SDRAMs? It would double capacity and bandwidth, but also allow an efficient 65Org32 one day. For the purposes of 65Org32, they would of course share an address bus.
(I've seen boards with the memory on the back side...)
Cheers
Ed

Hi Ed, the room is definately there now that I am loosing the MCP2200 and the mini-USB connector. I'll consider your suggestions, but I think this means I would have to switch the design to 32-bit entirely. I could still do what I want to do as far as this project is concerned but it would require me to put in the work for the 65Org32 core. Tempting...

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Mmm, no, you could add a second ram to the board but not hook it up to any core until a later date. It's just that if you don't add it to the board, you don't have the option. In other words, just use the low 16bits for now.
Cheers Ed

Yes a second SDRAM will fit easily on this...
EDIT: I think, though, that it would require a dedicated certain number of extra pins for the other 16-bits of the data bus, in order for the databus interface to interface to . I mean if I have a 16 bit system running, and I am expecting to run out of FPGA pins, surely the other 16 bits, IF it were the 65Org32 cpu onboard, would have to be dedicated in order for your idea to work. While there is space for double wide 16-bit wide data bus, a much more likely scenario, since another SDRAM fits, is to make it a 64MBx16 type system.
EDIT: Note that this video interface will require 16 more pins than the previous design. But there will be much more flexibility as far as chosen resolution, pixel clocks, and #of sprites...

The 96-pin main connector is a space hog! At least 1/5th of the boardspace is devoted to it. But 96 pins is enough for full address/data lines and 48 more signals (for the 65Org16).


That parallel FLASH does not have an old school interface I am looking for. I did find a 2Mx16 90ns FLASH for cheap (~$5US). Also, I think a couple 64Mbit (4Mx16) serial SPI FLASH's would fit on the back. These have been released recently and are cheap as well.

EDIT: I'm loosing the parallel FLASH, too many pins needed.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Hi EEye
Yes, pin budget on the FPGA is probably the limiting factor - could you perhaps tabulate what you currently have going in and out? It would be an interesting and compact overview.
Cheers
Ed

A quick count gives just over 100 pins.
Minus 6 pins dedicated for JTAG and FPGA Prom.
Minus 36 pins for 1 SDRAM.
Minus 24 pins for VideoDAC. EDIT: Minus 2 pins for HSYNC and VSYNC.
Minus 4 pins for 2 64Mbit serial SPI FLASH's. Plan on NC7SZ04M5X single inverter to invert /CE to 1 FLASH. This will save 1 pin from FPGA.

That leaves close to 30 pins. This might well be possible! This will leave me around 12 pins for other control signals I will need, which I think will be more than enough.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Thanks!
Is that 100 physical pins or signal pins - have you already accounted for power and ground?

These would be available signal pins. I am currently looking at V1.1 in EPCB which has been stripped of everything but FPGA and SDRAM.

But now as my thinking gets clearer, for a dedicated video board, I really don't need so much RAM. Maybe 2MB maximum. I'm thinking back to the Cypress 2Mx18 synchronous RAM I've seen before. Noone has them in stock...

I think I'll be concentrating on the SDRAM part of the project when I develop the master communications board. It would be nice too, to have the 65Org32 ready for this part.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Maybe I should find a schematic to check, but could you please split out the videodac and SDRAM into address control and data? Or point me at the best source so I can check!
Thanks

Edit: but it does sound feasible to squeeze 16 for a double width data bus

Ah, I may have missed something - you are now thinking of this as more purely a video board?

Yes, sorry. Was difficult to change my previous thinking of trying to fit everything on one board. It's actually easier to design one board at a time, each with it's own purpose. This will also help each dedicated core to maintain it's 100MHz speed.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

I was able to order 2 2Mx18 6.5ns synchronous RAMs directly from Cypress. All parts will be here next week, so I can measure dimensions in order to get this design right the first time. And it shouldn't take long to finish either. Not like the 4 months for the devboard v1.1!

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Hi EEye
Not sure what your plan is to make use of the pair of SPI flash memories, but it is possible to store multiple configs in a single flash and have a bootstrap design which chooses between them (I think)
See "Xilinx multiboot"
http://www.xilinx.com/support/documenta ... xtp059.pdf
http://www.xilinx.com/support/documenta ... df#page125

Cheers
Ed

I was planning on using the SPI serial FLASH as data/program storage not for FPGA boot. Using 2 of them may be overkill at 4MBx16 each, but I figured since they're so cheap and small 8-pin SOIC it couldn't hurt.

For the multiboot part of it, I was planning on 2 XCF04's. The TDO of the first would go into the TDI of the second. The TDO of the second would go into the TDI of the FPGA. iMPACT should see them both. Then the user could program either one.
The part I still need to figure out, especially if I would like to have another board select which one to boot from, is how to MUX the serial data stream to the FPGA without the use of jumpers. Looking for something smaller that 74157. Digikey doesn't seem to have MUXs in TinyLogic series.

EDIT: This is what I was looking for: 4mA & $.82 from NXP. A single 2:1 MUX in SOT-363 package.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502