To calibrate the Cyclone II LE count, we'd need to build several cores for it. Another metric would be the proportion of the FPGA a 6502 consumes - perhaps best expressed as dollar cost of the core.

It's notable that this thread dates back to fitting a Spartan 2 XC2S200 - that's a deal smaller than the smallest FPGA you'd buy today, I'd guess. (Not having shopped for small FPGAs.)

How old is the Cyclone II ? Spartan / Artix 7 are fairly new and have LUT's based on six inputs versus four inputs for older architectures. So designs naturally take fewer LUTs. It would take few more LUTs in an older chip. It sounds like a bit of Apples to Oranges comparisons going on perhaps. I like to use logic cells as a measure. The Xilinx maps LUTs to logic cells at a ratio of about 1.6:1. (Multiply the LUT count by 1.6 to get # of logic cells). I suspect there's a ratio for Altera Cyclone parts too. I've seen Cyclone IV parts advertised I think.

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Thanks for 1.6 - that's the kind of calibration one would need, I think, for each generation from each vendor. If anyone had the time and energy!

You may want to include this 6507 core in the comparison, which is kind of the same as a 6502: https://opencores.org/project/t6507lp

Interesting find: Verilog, and cycle-accurate. Last updated 2010 - but maybe it was finished - thanks for finding that and noting it here.

I think we (someone) needs to rerun the survey of results, because both the FPGAs and the toolchains have moved on a lot since this thread started. A new thread for Spartan 6, or for Lattice iCE40, would probably be the right way to go.

In both cases, you can get quite variable results: with Xilinx ISE using SmartExplorer and with Icestorm for Lattice using random seeds, there's more than 10% variation in results. To measure the quality of a design, you need to try various speed constraints and get several synthesis results. It's quite a bit of work.