Back at work again and things are slow, so I thought I would tackle the 'transfer with logic' again with the new accumulators.
I realized I needed a separate register that would contain the result of the logic functions AND, OR, XOR amongst the 4 Accumulators. The opcode names look like TABand, TABor, TABxor etc. in my As65 Macro's.
So this register called LOGOP (Logic Operator) I have working already with TABand and it takes 2 cycles. It may take 1 or more cycle to transfer it to the src_reg or dst_reg. Transferring this value will be the challenge for me at this point... I just finished all the other 4 Acc transfer + Logic.
If in the end these 'transfer with logic' opcodes slow down the core too much, I'll probably remove them. I am always concerned with speed, so we will see if a speed sacrifice is worth it, compared to cycles saved per instruction.
I intend to focus on this tradeoff, during this 65Org16.b Core expansion. If they prove good speedwise, then I'll look how to do the same 'transfer with logic' opcodes between the X & Y index registers, stack, and 4 accumulators.
Been thinking recently too, there needs to be a single cycle 16bit NOT (i.e. inverse) on any accumulator/index register.
Code:
always @(posedge clk)
if( state == DECODE && RDY )
casex( IR[15:0] )
16'b0000_xx01_1000_1011, // TABand, TABor, TABxor
16'b0000_xx00_1001_1011: // TBAand, TBAor, TBAxor
case( IR[11:10] )
2'b01: LOGOP <= ( DCBAXYS[SEL_A] & DCBAXYS[SEL_B] );
2'b10: LOGOP <= ( DCBAXYS[SEL_A] | DCBAXYS[SEL_B] );
2'b11: LOGOP <= ( DCBAXYS[SEL_A] ^ DCBAXYS[SEL_B] );
endcase
default:case( IR[11:8] )
4'b0001: LOGOP <= DCBAXYS[SEL_B]; //no LOGOP, send value to dest_reg
4'b0000: LOGOP <= DCBAXYS[SEL_A]; //no LOGOP, send value to dest_reg
endcase
endcase
Still working on the total opcode value list. Will post when they're all proven on Isim.